- rwrite(TIM4_PSC, PRESCALER - 1);
- presence_pulse_conf();
-// rwrite(TIM4_ARR, preload);
-// rsetbit(TIM4_EGR, 0);
-
- ivt_set_gate(46, init_handler, 0);
- rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
+// rsetbit(RCC_APB2ENR, 3); // GPIOB enable
+// rsetbit(RCC_APB1ENR, 2); // TIM4 enable
+//
+// rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
+// rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
+// rsetbit(TIM4_CR1, 2); // only overflow generates update
+//
+// rwrite(TIM4_PSC, PRESCALER - 1);
+// presence_pulse_conf();
+//// rwrite(TIM4_ARR, preload);
+//// rsetbit(TIM4_EGR, 0);
+//
+// ivt_set_gate(46, init_handler, 0);
+// rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
+//
+////w rsetbit(GPIOB_ODR, 6); //
+// rsetbit(TIM4_DIER, 0);
+// rsetbit(TIM4_CR1, 0); // start