1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/8/28 - ROBIN KRENS
8 * TIMERS, non-blocking...
17 #include <sys/robsys.h>
19 #include <lib/regfunc.h>
20 #include <lib/string.h>
21 #include <lib/tinyprintf.h>
23 #include <drivers/tsensor.h>
25 #define PRESCALER 8 // 1 MHz (1 microsecond)
29 enum status { INIT, WAIT_INIT, INIT_DONE } current_status;
30 enum rstatus { READ, READ_INIT, READ_DONE } read_status;
45 static void in_conf() {
46 rwrite(GPIOB_CRL, 0x44444444);
49 static void out_conf() {
50 rwrite(GPIOB_CRL, 0x46444444); // open drain (with pullup resistor)
53 /* set preload and generate update event */
54 static void timer_config(uint16_t preload) {
55 rwrite(TIM4_ARR, preload);
59 static void presence_pulse_conf() {
61 current_status = INIT;
63 rclrbit(GPIOB_ODR, 6); // low
64 timer_config(480); // > 480 us
67 static void presence_reply_conf() {
69 current_status = WAIT_INIT;
71 timer_config(60); // > 60 us
74 static void finish_init() {
75 current_status = INIT_DONE;
79 /* Handlers for read, write and init pulses */
81 void * write_handler() {
92 if (sensor_cmd.pos < 7) {
94 if ((sensor_cmd.cmd >> sensor_cmd.pos+1) & 0x01) {
102 rwrite(TIM4_CCR1, 60);
103 rsetbit(TIM4_EGR, 0);
115 void * reply_handler() {
123 rclrbit(TIM4_SR1, 0);
124 rclrbit(TIM4_SR1, 1);
125 switch(read_status) {
129 rsetbit(GPIOB_BSRR, 22); // low (<- reset)
130 if (rchkbit(GPIOB_IDR, 6)) {
140 rclrbit(GPIOB_ODR, 6); // low
141 read_status = READ_INIT;
156 rclrbit(TIM4_CR1, 0); // stop
157 rclrbit(TIM4_CCER, 0);
158 rclrbit(TIM4_CCER, 1);
160 //rwrite(GPIOB_CRL, 0x46444444); // floating
162 rsetbit(TIM4_CR1, 2); // only overflow generates update
163 read_status = READ_INIT;
164 timer_config(1); // init 1us
166 ivt_set_gate(46, reply_handler, 0);
167 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
169 //rclrbit(TIM4_DIER, 0);
171 rclrbit(GPIOB_ODR, 6); // low
172 rsetbit(TIM4_DIER, 0);
174 rsetbit(TIM4_CR1, 0);
181 sensor_cmd.cmd = 0x33;
184 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
185 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
186 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
187 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
188 rsetbit(TIM4_CR1, 2); // only overflow generates update
189 rwrite(TIM4_PSC, PRESCALER - 1);
190 rwrite(GPIOB_CRL, 0x4A444444);
195 if ((sensor_cmd.cmd >> sensor_cmd.pos) & 0x01) {
197 rwrite(TIM4_CCR1, 5); // < 15ms
201 rwrite(TIM4_CCR1, 60);
204 rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // forced high on match
206 rsetbit(TIM4_CCER, 0);
207 rsetbit(TIM4_CCER, 1);
210 ivt_set_gate(46, write_handler, 0);
211 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
213 //rsetbit(TIM4_DIER, 1);
214 rsetbit(TIM4_DIER, 0);
215 rsetbit(TIM4_CR1, 0);
220 void * init_handler() {
222 switch(current_status) {
224 printf("M: reset\n");
225 presence_reply_conf();
228 if (!rchkbit(GPIOB_IDR, 6)) {
243 printf("no status\n");
246 rclrbit(TIM4_SR1, 0);
256 * read, similar as pulse response */
259 void * bare_handler() {
262 //w2 printf("CHECKING STATUS\n");
264 //w2 if(rchkbit(GPIOB_IDR, 6)) {
265 //w2 printf("port high\n");
268 //w2 printf("port low\n");
273 printf("Count event %d\n", cnt);
274 int switchled = cnt % 2;
276 rwrite(GPIOB_CRL, 0x46444444); // open drain general for sensor?
277 printf("setting low\n");
278 rclrbit(GPIOB_ODR, 6); // low
281 printf("pulling high \n");
282 rwrite(GPIOB_CRL, 0x44444444); // open drain general for sensor?
283 //rsetbit(GPIOB_ODR, 6); // high
286 rclrbit(TIM4_SR1, 0);
289 void send_cmd(unsigned char cmd) {
294 for (int i = 0; i < 8; i++) {
296 rclrbit(GPIOB_ODR, 6);
297 if ((cmd >> pos) & 0x01) {
314 for (int i = 0; i < 64; i++) {
316 rclrbit(GPIOB_ODR, 6);
319 if (rchkbit(GPIOB_IDR,6))
331 void tsensor_init() {
333 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
335 rclrbit(GPIOB_ODR, 6); // loq
339 if (!rchkbit(GPIOB_IDR, 6)) {
348 // rsetbit(RCC_APB2ENR, 3); // GPIOB enable
349 // rsetbit(RCC_APB1ENR, 2); // TIM4 enable
351 // rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
352 // rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
353 // rsetbit(TIM4_CR1, 2); // only overflow generates update
355 // rwrite(TIM4_PSC, PRESCALER - 1);
356 // presence_pulse_conf();
357 //// rwrite(TIM4_ARR, preload);
358 //// rsetbit(TIM4_EGR, 0);
360 // ivt_set_gate(46, init_handler, 0);
361 // rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
363 ////w rsetbit(GPIOB_ODR, 6); //
364 // rsetbit(TIM4_DIER, 0);
365 // rsetbit(TIM4_CR1, 0); // start
369 void wait_for_sensor() {
372 rclrbit(GPIOB_ODR, 6);
375 while (!rchkbit(GPIOB_IDR, 6)) {
379 rclrbit(GPIOB_ODR, 6);
388 //w2 rsetbit(RCC_APB2ENR, 3);
389 //w2 rwrite(GPIOB_CRL, 0x48444444); // input with pull up down
390 //w2 tsensor_simple(5000);
393 //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
394 //rwrite(GPIOB_CRL, 0x46444444); // open drain general for sensor?
396 //rsetbit(GPIOB_BSRR, 22); // low (<- reset)
417 // tsensor_output(580, 520);
419 // tsensor_simple(580);
422 //void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
423 // /* GPIO AND CLOCK */
424 // rsetbit(RCC_APB2ENR, 3); // GPIOB enable
425 // rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
426 // rsetbit(RCC_APB1ENR, 2); // TIM4 enable
428 // rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
429 // rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
430 // rsetbit(TIM4_CR1, 2); // only overflow generates update
432 // rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
433 // rwrite(TIM4_ARR, preload); // preload
434 // rwrite(TIM4_CCR1, compare); // compare
435 // //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
437 // rsetbit(TIM4_EGR, 0); // update generation
439 // rsetbit(TIM4_CR1, 3); // one pulse mode
440 // rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
442 // //rsetbit(TIM4_CCMR1, 3); // preload enable
443 // //rsetbit(TIM4_CR1, 7); // buffered
445 // rsetbit(TIM4_CCER, 0); // enable output channeli 1
446 // rsetbit(TIM4_CCER, 1); // active low
447 // rsetbit(TIM4_CR1, 0); // start counter
450 // ivt_set_gate(46, tmp_update_handler, 0);
452 // rsetbit(TIM4_DIER, 1);
453 // rsetbit(NVIC_ISER0, 30); // interupt 41 - 32