-void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
-
- /* GPIO AND CLOCK */
- rsetbit(RCC_APB2ENR, 3); // GPIOB enable
- rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
- rsetbit(RCC_APB1ENR, 2); // TIM4 enable
-
- rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
- rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
- rsetbit(TIM4_CR1, 2); // only overflow generates update
-
- rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
- rwrite(TIM4_ARR, preload); // preload
- rwrite(TIM4_CCR1, compare); // compare
- //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
-
- rsetbit(TIM4_EGR, 0); // update generation
-
- rsetbit(TIM4_CR1, 3); // one pulse mode
- rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
-
- //rsetbit(TIM4_CCMR1, 3); // preload enable
- //rsetbit(TIM4_CR1, 7); // buffered
-
- rsetbit(TIM4_CCER, 0); // enable output channeli 1
- rsetbit(TIM4_CCER, 1); // active low
- rsetbit(TIM4_CR1, 0); // start counter
-
- /* INTERRUPTS */
- ivt_set_gate(46, tmp_update_handler, 0);
-
- rsetbit(TIM4_DIER, 1);
- rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
-
-}
-
-void tsensor_input(uint16_t preload) {
-
- //uint16_t timestamp;
- /* GPIO AND CLOCK */
- //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
- //rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
- //rsetbit(RCC_APB1ENR, 2); // TIM4 enable
-
- //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
- //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
-
- rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
- rwrite(TIM4_ARR, preload); // preload
-
-
- rsetbit(TIM4_EGR, 0); // update generation
-
- rsetbit(TIM4_CCMR1, 0); // input on TI1
- rsetbit(TIM4_CCMR1, 9); // another input TI2
- rsetbit(TIM4_CCER, 1); // other polarity for T1, inverted
-
- /* TODO: reg funct */
- rsetbit(TIM4_SMCR, 4); // OLD: 101, new Edge detector
- rsetbit(TIM4_SMCR, 6); //
-
-
- // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
- rsetbit(TIM4_SMCR, 2); // OLD: 110
- rsetbit(TIM4_SMCR, 1);
- rsetbit(TIM4_SMCR, 0);
- //rsetbit(TIM4_SMCR, 1); // 110
-
- //rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
- // will catch multiple signal... can set fram
-
- rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
- rsetbit(TIM4_CCER, 4); // enable capture channel 2
- /* Caught on rising edge, no need to change*/
- /* Clear capture event flag */
-// rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
-
- // enable capture channel 1 interrupt
- rsetbit(TIM4_DIER, 1);
- rsetbit(TIM4_DIER, 2);
- ivt_set_gate(46, update_handler, 0);
- rsetbit(NVIC_ISER0, 30);
-
-}
+//void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
+// /* GPIO AND CLOCK */
+// rsetbit(RCC_APB2ENR, 3); // GPIOB enable
+// rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
+// rsetbit(RCC_APB1ENR, 2); // TIM4 enable
+//
+// rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
+// rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
+// rsetbit(TIM4_CR1, 2); // only overflow generates update
+//
+// rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
+// rwrite(TIM4_ARR, preload); // preload
+// rwrite(TIM4_CCR1, compare); // compare
+// //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
+//
+// rsetbit(TIM4_EGR, 0); // update generation
+//
+// rsetbit(TIM4_CR1, 3); // one pulse mode
+// rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
+//
+// //rsetbit(TIM4_CCMR1, 3); // preload enable
+// //rsetbit(TIM4_CR1, 7); // buffered
+//
+// rsetbit(TIM4_CCER, 0); // enable output channeli 1
+// rsetbit(TIM4_CCER, 1); // active low
+// rsetbit(TIM4_CR1, 0); // start counter
+//
+// /* INTERRUPTS */
+// ivt_set_gate(46, tmp_update_handler, 0);
+//
+// rsetbit(TIM4_DIER, 1);
+// rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
+//
+//}