+ uint16_t timestamp;
+ /* GPIO AND CLOCK */
+ rsetbit(RCC_APB2ENR, 3); // GPIOB enable
+ rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
+ rsetbit(RCC_APB1ENR, 2); // TIM4 enable
+
+ //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
+ //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
+
+ rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
+ rwrite(TIM4_ARR, preload); // preload
+
+ rsetbit(TIM4_CCMR1, 0); // input on TI1
+ rsetbit(TIM4_CCMR1, 9); // another input TI2
+ rsetbit(TIM4_CCER, 5); // other polarity, inverted
+
+ /* TODO: reg funct */
+ rsetbit(TIM4_SMCR, 4); // 101
+ rsetbit(TIM4_SMCR, 6); // 101
+
+
+
+ // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
+ rsetbit(TIM4_SMCR, 2); // 110
+ rsetbit(TIM4_SMCR, 1); // 110
+
+ rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
+ // will catch multiple signal... can set fram
+
+ rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
+ rsetbit(TIM4_CCER, 4); // enable capture channel 2
+ /* Caught on rising edge, no need to change*/
+ /* Clear capture event flag */
+// rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
+
+ // enable capture channel 1 interrupt
+ rsetbit(TIM4_DIER, 1);
+ rsetbit(TIM4_DIER, 2);
+ ivt_set_gate(46, update_handler, 0);
+ rsetbit(NVIC_ISER0, 30);
+
+}