1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/8/4 - ROBIN KRENS
17 #include <sys/robsys.h>
19 #include <lib/regfunc.h>
20 #include <lib/string.h>
21 #include <lib/tinyprintf.h>
23 #include <drivers/tsensor.h>
25 #define PRESCALER 36000 // 1 kHz
27 void * update_handler() {
29 if(rchkbit(TIM4_SR1, 1)) {
31 printf("RISING EDGE CAUGHT\n");
32 printf("CCR1: %p\n", *TIM4_CCR1);
35 if(rchkbit(TIM4_SR1, 2)) {
36 printf("FALLING EDGE CAUGHT\n");
37 printf("CCR2: %p\n", *TIM4_CCR2);
43 rclrbit(TIM4_SR1, 2); //
44 rclrbit(TIM4_SR1, 9); // OF
45 rclrbit(TIM4_SR1, 10); // OF
47 // TODO clear overflow tag
50 void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
53 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
54 rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
55 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
57 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
58 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
60 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
61 rwrite(TIM4_ARR, preload); // preload
62 rwrite(TIM4_CCR1, compare); // compare
63 //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
65 rsetbit(TIM4_EGR, 0); // update generation
67 rsetbit(TIM4_CR1, 3); // one pulse mode
68 rsetbitsfrom(TIM4_CCMR1, 4, 0x7); // PWM mode 1
70 //rsetbit(TIM4_CCMR1, 3); // preload enable
71 //rsetbit(TIM4_CR1, 7); // buffered
74 rsetbit(TIM4_CCER, 0); // enable output channel 1
75 rsetbit(TIM4_CR1, 0); // start counter
78 //ivt_set_gate(41, update_handler, 0);
80 //rsetbit(TIM4_DIER, 0);
81 //rsetbit(NVIC_ISER0, 25); // interupt 41 - 32
84 void tsensor_input(uint16_t preload) {
88 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
89 rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
90 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
92 //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
93 //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
95 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
96 rwrite(TIM4_ARR, preload); // preload
98 rsetbit(TIM4_CCMR1, 0); // input on TI1
99 rsetbit(TIM4_CCMR1, 9); // another input TI2
100 rsetbit(TIM4_CCER, 5); // other polarity, inverted
102 /* TODO: reg funct */
103 rsetbit(TIM4_SMCR, 4); // 101
104 rsetbit(TIM4_SMCR, 6); // 101
108 // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
109 rsetbit(TIM4_SMCR, 2); // 110
110 rsetbit(TIM4_SMCR, 1); // 110
112 rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
113 // will catch multiple signal... can set fram
115 rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
116 rsetbit(TIM4_CCER, 4); // enable capture channel 2
117 /* Caught on rising edge, no need to change*/
118 /* Clear capture event flag */
119 // rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
121 // enable capture channel 1 interrupt
122 rsetbit(TIM4_DIER, 1);
123 rsetbit(TIM4_DIER, 2);
124 ivt_set_gate(46, update_handler, 0);
125 rsetbit(NVIC_ISER0, 30);