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hbc: timer with compare match output
author
Robin Krens
<robin@robinkrens.nl>
Thu, 19 May 2022 14:52:53 +0000
(16:52 +0200)
committer
Robin Krens
<robin@robinkrens.nl>
Thu, 19 May 2022 14:52:53 +0000
(16:52 +0200)
hbc.c
patch
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diff --git
a/hbc.c
b/hbc.c
index
d0169bd
..
5ff04c7
100644
(file)
--- a/
hbc.c
+++ b/
hbc.c
@@
-14,14
+14,18
@@
volatile int xvar = 1;
* return PC after latest sleep_mode() call */
EMPTY_INTERRUPT(SIG_COMPARATOR);
* return PC after latest sleep_mode() call */
EMPTY_INTERRUPT(SIG_COMPARATOR);
-ISR(TIM0_OVF_vect)
+ISR(TIM0_COMPA_vect)
+{
+ xvar++;
+}
+ISR(TIM0_COMPB_vect)
{
xvar++;
}
{
xvar++;
}
-/* for debugging purposes */
-ISR(BADISR_vect)
+ISR(TIM0_OVF_vect)
{
{
+ //xvar++;
}
}
@@
-43,19
+47,20
@@
static void init_board(void)
int main(void)
{
int main(void)
{
-
init_board();
init_board();
-
- xvar = 1;
+ xvar = 1;
cli();
cli();
- TCCR0A = 0x00;
- TCCR0B = (1 << CS00) | (1 << CS02);
+ DDRB |= (1 << DDB0); /* set PB0 as output */
+ TCCR0A = TCCR0B = 0;
+ TCCR0A |= (1 << WGM01) | (1 << WGM00) | (1 << COM0A1);
+ TCCR0B |= (1 << CS02) | (1 << CS00); /* clk/1024 prescaler */
+ OCR0A = 0x7F; /* 50% duty cycle */
TCNT0 = 0;
TCNT0 = 0;
- TIMSK
|= (1 << TOIE0);
+ TIMSK
= (1 << OCIE0A) | (1 << OCIE0B) | (1 << TOIE0); /* enable interrupts for overflow and compare */
sei();
while(1) {
sei();
while(1) {
-
+ _delay_ms(100);
/* set LRA as sensor and switch to idle mode
* check back-EMF of LRA: if treshold is surpassed
* comparator intterupt is triggered */
/* set LRA as sensor and switch to idle mode
* check back-EMF of LRA: if treshold is surpassed
* comparator intterupt is triggered */