1 ;--------------------------------------------
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2 ; Wonderswan Registers & Equates v0.2
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5 ; http://onorisoft.free.fr/
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7 ; with help of WStech24.txt by Judge and Dox
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8 ;--------------------------------------------
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10 ; IO_ mean byte access
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11 ; IOw_ mean word access
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17 RH_ROM_4MBITS equ 0x02
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18 RH_ROM_8MBITS equ 0x03
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19 RH_ROM_16MBITS equ 0x04
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20 RH_ROM_32MBITS equ 0x06
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21 RH_ROM_64MBITS equ 0x08
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22 RH_ROM_128MBITS equ 0x09
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25 RH_SRAM_64KBITS equ 0x01
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26 RH_SRAM_256KBITS equ 0x02
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27 RH_SRAM_1MBITS equ 0x03
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28 RH_SRAM_2MBITS equ 0x04
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29 RH_SRAM_1KBITS equ 0x10
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30 RH_SRAM_16KBITS equ 0x20
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31 RH_SRAM_8KBITS equ 0x50
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34 RH_WS_COLOR equ 0x01
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39 RH_HORIZONTAL equ (0x04 + 0x00)
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40 RH_VERTICAL equ (0x04 + 0x01)
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47 WS_RAM_BASE equ 0x0000
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48 WS_TILE_BANK equ 0x2000
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49 WS_STACK equ WS_TILE_BANK-2
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51 WSC_TILE_BANK1 equ 0x4000
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52 WSC_TILE_BANK2 equ 0x8000
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53 WSC_RAM_BASE2 equ 0xC000
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54 WSC_PALETTES equ 0xFE00
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55 WSC_STACK equ WSC_PALETTES-2
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58 SPR_TABLE_SIZE equ 0x200
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65 INTVEC_HBLANK_TIMER equ 7
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66 INTVEC_VBLANK_START equ 6
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67 INTVEC_VBLANK_TIMER equ 5
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68 INTVEC_DRAWING_LINE equ 4
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69 INTVEC_SERIAL_RECEIVE equ 3
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70 INTVEC_RTC_ALARM equ 2
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71 INTVEC_KEY_PRESS equ 1
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72 INTVEC_SERIAL_SEND equ 0
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79 %define BG_CHR(tile,pal,bank,hflip,vflip) (((vflip) << 15) | ((hflip) << 14) | ((bank) << 13) | ((pal) << 9) | (tile))
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81 %macro ROM_HEADER 7 ; Label, Segment, DevID, WSType, RomSize, SRamSize, WSSpec
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82 times ((64*1024)-16)-$+%1 db 0xFF
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89 db %3 ; Developer ID
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91 db 0x01 ; Cart number
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97 dw 0x0000 ; Checksum
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100 %macro PADDING 1 ; Number of Segment
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101 times (%1*64*1024) db 0xFF
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104 SCREEN_WIDTH equ 224
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105 SCREEN_HEIGHT equ 144
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106 SCREEN_TWIDTH equ (SCREEN_WIDTH / 8)
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107 SCREEN_THEIGHT equ (SCREEN_HEIGHT / 8)
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110 MAP_TWIDTH equ (MAP_WIDTH / 8)
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111 MAP_THEIGHT equ (MAP_HEIGHT / 8)
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115 ;-----------------------------------
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116 ; I/O Ports and associated equates
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118 IO_DISPLAY_CTRL equ 0x00
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125 SPR_WIN_ON equ 0x08
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126 SPR_WIN_OFF equ 0x00
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127 FG_IN_OUT_WIN equ 0x00
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129 FG_OUT_WIN equ 0x30
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132 %define BG_COLOR(a) (a)
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133 %define BG_PAL(a) (a << 4)
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135 IO_CUR_LINE equ 0x02
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136 IO_LINE_COMP equ 0x03
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138 IO_SPR_TABLE equ 0x04
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139 %define SPR_TABLE(a) (a >> 9) ; Sprite Table Address must be 512 bytes aligned !
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141 IO_SPR_START equ 0x05
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142 IO_SPR_STOP equ 0x06
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144 IO_FGBG_MAP equ 0x07
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145 %define FG_MAP(a) ((a >> 11) << 4) ; FG Map Address must be 2048 bytes aligned !
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146 %define BG_MAP(a) (a >> 11) ; BG Map Address must be 2048 bytes aligned !
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148 IO_FG_WIN_X0 equ 0x08
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149 IO_FG_WIN_Y0 equ 0x09
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150 IO_FG_WIN_X1 equ 0x0A
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151 IO_FG_WIN_Y1 equ 0x0B
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153 IO_SPR_WIN_X0 equ 0x0C
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154 IO_SPR_WIN_Y0 equ 0x0D
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155 IO_SPR_WIN_X1 equ 0x0E
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156 IO_SPR_WIN_Y1 equ 0x0F
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164 IO_LCD_CTRL equ 0x14
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168 IO_LCD_ICONS equ 0x15
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169 LCD_ICON_SLEEP equ 0x01
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170 LCD_ICON_VERTI equ 0x02
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171 LCD_ICON_HORIZ equ 0x04
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172 LCD_ICON_DOT1 equ 0x08
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173 LCD_ICON_DOT2 equ 0x10
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174 LCD_ICON_DOT3 equ 0x20
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176 IO_PALSHADE_10 equ 0x1C
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177 IO_PALSHADE_32 equ 0x1D
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178 IO_PALSHADE_54 equ 0x1E
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179 IO_PALSHADE_76 equ 0x1F
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181 IO_WS_PAL_00 equ 0x20
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182 IO_WS_PAL_01 equ 0x21
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183 IO_WS_PAL_10 equ 0x22
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184 IO_WS_PAL_11 equ 0x23
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185 IO_WS_PAL_20 equ 0x24
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186 IO_WS_PAL_21 equ 0x25
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187 IO_WS_PAL_30 equ 0x26
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188 IO_WS_PAL_31 equ 0x27
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189 IO_WS_PAL_40 equ 0x28
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190 IO_WS_PAL_41 equ 0x29
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191 IO_WS_PAL_50 equ 0x2A
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192 IO_WS_PAL_51 equ 0x2B
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193 IO_WS_PAL_60 equ 0x2C
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194 IO_WS_PAL_61 equ 0x2D
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195 IO_WS_PAL_70 equ 0x2E
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196 IO_WS_PAL_71 equ 0x2F
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197 IO_WS_PAL_80 equ 0x30
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198 IO_WS_PAL_81 equ 0x31
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199 IO_WS_PAL_90 equ 0x32
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200 IO_WS_PAL_91 equ 0x33
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201 IO_WS_PAL_A0 equ 0x34
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202 IO_WS_PAL_A1 equ 0x35
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203 IO_WS_PAL_B0 equ 0x36
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204 IO_WS_PAL_B1 equ 0x37
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205 IO_WS_PAL_C0 equ 0x38
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206 IO_WS_PAL_C1 equ 0x39
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207 IO_WS_PAL_D0 equ 0x3A
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208 IO_WS_PAL_D1 equ 0x3B
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209 IO_WS_PAL_E0 equ 0x3C
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210 IO_WS_PAL_E1 equ 0x3D
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211 IO_WS_PAL_F0 equ 0x3E
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212 IO_WS_PAL_F1 equ 0x3F
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214 IOw_DMA_SRC equ 0x40
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215 IO_DMA_SRC_BANK equ 0x42
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216 IO_DMA_DST_BANK equ 0x43
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217 IOw_DMA_DST equ 0x44
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218 IOw_DMA_SIZE equ 0x46
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219 IO_DMA_CTRL equ 0x48
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223 IOw_SNDDMA_SRC equ 0x4A
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224 IO_SNDDMA_BANK equ 0x4C
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225 IOw_SNDDMA_SIZE equ 0x4E
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226 IO_SNDDMA_CTRL equ 0x52
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228 IO_VIDEO_MODE equ 0x60
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229 VMODE_16C_CHK equ 0xE0 ; 16 colors per tile chunky mode
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230 VMODE_16C_PLN equ 0xC0 ; 16 colors per tile planar mode
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231 VMODE_4C equ 0x40 ; 4 colors per tile color
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232 VMODE_4C_MONO equ 0x00 ; 4 colors per tile mono
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233 VMODE_CLEANINIT equ 0x0C ; (?) from FF2
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235 IOw_AUDIO1_FREQ equ 0x80 ; Frequency
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236 IOw_AUDIO2_FREQ equ 0x82
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237 IOw_AUDIO3_FREQ equ 0x84
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238 IOw_AUDIO4_FREQ equ 0x86
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240 IO_AUDIO1_VOL equ 0x88 ; Volume
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241 IO_AUDIO2_VOL equ 0x89
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242 IO_AUDIO3_VOL equ 0x8A
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243 IO_AUDIO4_VOL equ 0x8B
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245 IO_AUDIO_SWEEP_VAL equ 0x8C
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246 IO_AUDIO_SWEEP_STEP equ 0x8D
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248 IO_AUDIO_NOISE_CTRL equ 0x8E
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249 %define NOISE_TYPE(a) (a)
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250 NOISE_RESET equ 0x08
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251 NOISE_ENABLE equ 0x10
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253 IO_AUDIO_SAMPLE equ 0x8F ; Sample location
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254 %define AUDIO_SAMPLE(a) (a >> 6)
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256 IO_AUDIO_CTRL equ 0x90
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257 AUDIO_1_ON equ 0x01
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258 AUDIO_1_OFF equ 0x00
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259 AUDIO_2_ON equ 0x02
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260 AUDIO_2_OFF equ 0x00
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261 AUDIO_3_ON equ 0x04
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262 AUDIO_3_OFF equ 0x00
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263 AUDIO_4_ON equ 0x08
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264 AUDIO_4_OFF equ 0x00
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265 AUDIO_2_VOICE equ 0x20
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266 AUDIO_3_SWEEP equ 0x40
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267 AUDIO_4_NOISE equ 0x80
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269 IO_AUDIO_OUTPUT equ 0x91
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270 AUDIO_OUT_MONO equ 0x01
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271 AUDIO_OUT_STEREO equ 0x08
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272 %define AUDIO_OUT_VOLUME(a) ((a & 0x03) << 1)
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274 IOw_AUDIO_NOISE_CNT equ 0x92
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275 IO_AUDIO_VOLUME equ 0x94 ; Global Volume (4 bits)
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277 IO_HARDWARE_TYPE equ 0xA0
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281 IO_TIMER_CTRL equ 0xA2
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282 HBLANK_TIMER_ON equ 0x01
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283 HBLANK_TIMER_OFF equ 0x00
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284 HBLANK_TIMER_MODE_ONESHOT equ 0x00
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285 HBLANK_TIMER_MODE_AUTOPRESET equ 0x02
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286 VBLANK_TIMER_ON equ 0x04
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287 VBLANK_TIMER_OFF equ 0x00
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288 VBLANK_TIMER_MODE_ONESHOT equ 0x00
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289 VBLANK_TIMER_MODE_AUTOPRESET equ 0x08
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291 IOw_HBLANK_FREQ equ 0xA4
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292 IOw_VBLANK_FREQ equ 0xA6
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294 IO_HBLANK_CNT1 equ 0xA8 ; Hblank Counter - 1/12000s
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295 IO_HBLANK_CNT2 equ 0xA9 ; Hblank Counter - 1/(12000>>8)s
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296 IO_VBLANK_CNT1 equ 0xAA ; Vblank Counter - 1/75s
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297 IO_VBLANK_CNT2 equ 0xAB ; Vblank Counter - 1/(75>>8)s
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299 IO_INT_BASE equ 0xB0
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302 IO_COMM_DATA equ 0xB1 ; Communication byte
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304 IO_INT_ENABLE equ 0xB2
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305 INT_HBLANK_TIMER equ 0x80
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306 INT_VBLANK_START equ 0x40
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307 INT_VBLANK_TIMER equ 0x20
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308 INT_DRAWING_LINE equ 0x10
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309 INT_SERIAL_RECEIVE equ 0x08
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310 INT_RTC_ALARM equ 0x04
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311 INT_KEY_PRESS equ 0x02
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312 INT_SERIAL_SEND equ 0x01
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314 IO_COMM_DIR equ 0xB3 ; Communication direction
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315 COMM_RECEIVE_INT_GEN equ 0x80
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316 COMM_SPEED_9600 equ 0x00
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317 COMM_SPEED_38400 equ 0x40
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318 COMM_SEND_INT_GEN equ 0x20
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319 COMM_SEND_COMPLETE equ 0x04
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320 COMM_ERROR equ 0x02
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321 COMM_RECEIVE_COMPLETE equ 0x01
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324 KEYPAD_READ_ARROWS_V equ 0x10
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325 KEYPAD_READ_ARROWS_H equ 0x20
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326 KEYPAD_READ_BUTTONS equ 0x40
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335 IO_INT_ACK equ 0xB6 ; See IO_INT_ENABLE equates for values
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337 IOw_INTERNAL_EEPROM_DATA equ 0xBA
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338 IOw_INTERNAL_EEPROM_ADDRESS equ 0xBC
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340 IOw_INTERNAL_EEPROM_CTRL equ 0xBE
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341 IEEPROM_INIT equ 0x80
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342 IEEPROM_PROTECT equ 0x40
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343 IEEPROM_WRITE equ 0x20
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344 IEEPROM_READ equ 0x10
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345 IEEPROM_WRITE_COMPLETE equ 0x02
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346 IEEPROM_READ_COMPLETE equ 0x01
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348 IO_ROM_BASE_BANK equ 0xC0
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349 IO_SRAM_BANK equ 0xC1
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350 IO_ROM_BANK_SEGMENT2 equ 0xC2
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351 IO_ROM_BANK_SEGMENT3 equ 0xC3
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353 IO_RTC_COMMAND equ 0xCA
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354 RTC_COMMAND_RESET equ 0x10
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355 RTC_COMMAND_ALARM equ 0x12
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356 RTC_COMMAND_SET_TIME equ 0x14
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357 RTC_COMMAND_GET_TIME equ 0x15
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358 RTC_COMMAND_ACK equ 0x80
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360 IO_RTC_DATA equ 0xCB
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