3 * Author : Robin Krens <robin@robinkrens.nl>
5 * Last Modified Date: 22.01.2023
6 * Last Modified By : Robin Krens <robin@robinkrens.nl>
10 #define SI24_R_REGISTER 0x00
11 #define SI24_W_REGISTER 0x20
12 #define SI24_R_RX_PAYLOAD 0x61
13 #define SI24_W_TX_PAYLOAD 0xA0
14 #define SI24_FLUSH_TX 0xE1
15 #define SI24_FLUSH_RX 0xE2
16 #define SI24_REUSE_TX_PL 0xE3
17 #define SI24_RX_PL_WID 0x60
18 #define SI24_W_ACK_PAYLOAD 0xA8
19 #define SI24_W_TX_PAYLOAD_NO_ACK 0xB0
22 /* SI24R1 register addresses */
23 #define SI24_REG_CONFIG 0x00
24 #define SI24_REG_EN_AA 0x01
25 #define SI24_REG_EN_RXADDR 0x02
26 #define SI24_REG_SETUP_AW 0x03
27 #define SI24_REG_SETUP_RETR 0x04
28 #define SI24_REG_RF_CH 0x05
29 #define SI24_REG_RF_SETUP 0x06
30 #define SI24_REG_STATUS 0x07
31 #define SI24_REG_OBSERVE_TX 0x08
32 #define SI24_REG_RSSI 0x09
33 #define SI24_REG_RX_ADDR_P0 0x0A
34 #define SI24_REG_RX_ADDR_P1 0x0B
35 #define SI24_REG_RX_ADDR_P2 0x0C
36 #define SI24_REG_RX_ADDR_P3 0x0D
37 #define SI24_REG_RX_ADDR_P4 0x0E
38 #define SI24_REG_RX_ADDR_P5 0x0F
39 #define SI24_REG_TX_ADDR 0x10
40 #define SI24_REG_RX_PW_P0 0x11
41 #define SI24_REG_RX_PW_P1 0x12
42 #define SI24_REG_RX_PW_P2 0x13
43 #define SI24_REG_RX_PW_P3 0x14
44 #define SI24_REG_RX_PW_P4 0x15
45 #define SI24_REG_RX_PW_P5 0x16
46 #define SI24_REG_FIFO_SATUS 0x17
47 #define SI24_REG_DYNPD 0x1C
48 #define SI24_REG_FEATURE 0x1D
55 #define MASK_MAX_RT 0x4
56 #define MASK_TX_DS 0x5
57 #define MASK_RX_DR 0x6
77 #define ARD(x) ((x << 3) & 0xF0)
78 #define ARC(x) (x & 0xF)
83 #define RF_DR_HIGH 0x03
85 #define RF_DR_LOW 0x05
86 #define CONT_WAVE 0x07
88 #define PLOS_CNT(x) (x & 0xF0)
89 #define ARC_CNT(x) (x & 0x0F)
105 #define EN_DYN_ACK 0x0
106 #define EN_ACK_PAY 0x1
113 unsigned _RESERVED:1;