3 * Author : Robin Krens <robin@robinkrens.nl>
5 * Last Modified Date: 22.01.2023
6 * Last Modified By : Robin Krens <robin@robinkrens.nl>
16 #include "libsi24reg.h"
19 #define TIMEOUT 0xFFFF
22 const si24_opts_t *opts;
23 const si24_ioctl_t *ctl;
24 si24_event_handler_t eh;
27 static uint8_t _reg_read(si24_t *si, uint8_t reg,
28 uint8_t *data, int sz)
33 buf[0] = reg | SI24_R_REGISTER;
36 if (si->ctl->write_and_read(buf, sz+1) == -1) {
43 memcpy(data, (buf+1), sz);
48 static uint8_t _reg_write(si24_t *si, uint8_t reg,
49 const uint8_t *data, int sz)
53 buf[0] = reg | SI24_W_REGISTER;
54 memcpy((buf+1), data, sz);
57 printf("REG 0x%x:\t", reg);
58 for (int i = 1; i <= sz; ++i) {
59 fprintf(stdout, "0x%x(%c)", buf[i], buf[i]);
61 fprintf(stdout, "\n");
64 if (si->ctl->write_and_read(buf, sz+1) == -1) {
74 static int _config(si24_t * si)
77 uint8_t config_reg = (1 << PWR_UP);
78 uint8_t feature_reg = 0x0; /* default value */
79 uint8_t rf_setup_reg = 0xE; /* default value */
80 uint8_t setup_retr_reg = 0x3; /* default value */
81 const uint8_t rf_ch_reg = 0x40; /* default value */
82 const si24_opts_t * params = si->opts;
84 if (params->enable_crc) {
85 config_reg |= (1 << EN_CRC);
86 config_reg |= (si->opts->crc << CRCO);
89 if (params->enable_ack) {
90 if (params->mode == SEND_MODE) {
91 setup_retr_reg = ARD(params->timeout) | ARC(params->retries);
92 ret += _reg_write(si, SI24_REG_SETUP_RETR, &setup_retr_reg, 1);
95 if (params->mode == SEND_MODE) {
96 feature_reg |= (1 << EN_DYN_ACK);
97 ret += _reg_write(si, SI24_REG_FEATURE, &feature_reg, 1);
101 if (params->enable_dynpd) {
102 uint8_t dyn = (1 << DPL_P0);
103 ret += _reg_write(si, SI24_REG_DYNPD, &dyn, 1);
104 feature_reg |= (1 << EN_DPL);
105 ret += _reg_write(si, SI24_REG_FEATURE, &feature_reg, 1);
106 } else { /* fixed payload size */
107 if (params->mode == RECV_MODE) {
108 ret += _reg_write(si, SI24_REG_RX_PW_P0, (uint8_t *) ¶ms->payload, 1);
113 ret += _reg_write(si, SI24_REG_SETUP_AW, &aw, 1);
115 if (params->mode == SEND_MODE && params->enable_ack) {
116 ret += _reg_write(si, SI24_REG_RX_ADDR_P0, params->mac_addr, sizeof(params->mac_addr));
119 if (params->mode == RECV_MODE) {
120 config_reg |= (1 << PRIM_RX);
122 ret += _reg_write(si, SI24_REG_EN_RXADDR, &ch, 1);
123 ret += _reg_write(si, SI24_REG_RX_ADDR_P0, params->mac_addr, sizeof(params->mac_addr));
125 ret += _reg_write(si, SI24_REG_TX_ADDR, params->mac_addr, sizeof(params->mac_addr));
128 rf_setup_reg |= (params->speed << RF_DR_HIGH);
129 rf_setup_reg |= (params->txpwr << RF_PWR);
130 ret += _reg_write(si, SI24_REG_RF_SETUP, &rf_setup_reg, 1);
133 ret += _reg_write(si, SI24_REG_RF_CH, &rf_ch_reg, 1);
134 ret += _reg_write(si, SI24_REG_CONFIG, &config_reg, 1);
136 if (params->mode == RECV_MODE) {
137 /* start accepting data immediately,
138 * for send mode it is onyl activated upon sending */
139 params->ioctl->chip_enable(1);
145 si24_t* si24_init(const si24_opts_t *opts, si24_event_handler_t eh)
147 struct si24_t *si = (si24_t*) calloc(1, sizeof(si24_t));
152 si->ctl = opts->ioctl;
155 int ret = _config(si);
164 size_t si24_send(si24_t* si, const unsigned char * buf, size_t size)
167 size_t bytes_sent = 0;
168 uint16_t timeout = 0;
172 if (si->opts->mode == RECV_MODE)
175 _reg_read(si, SI24_REG_STATUS, (uint8_t *) &flags, 1);
177 if (flags & (1 << TX_FULL)) {
178 ev.type = EV_TX_FULL;
183 int payload = si->opts->payload;
185 if (si->opts->enable_dynpd)
186 payload = size > 32 ? 32 : size;
188 for (size_t idx = 0; idx < size; idx += payload) {
189 sz = (size - idx) < payload ? (size - idx) : payload;
190 if (si->opts->enable_ack) {
191 _reg_write(si, SI24_W_TX_PAYLOAD, buf + idx, sz);
192 si->ctl->chip_enable(1);
193 while ((!(flags & (1 << TX_DS)) && !(flags & (1 << MAX_RT))) && timeout < TIMEOUT) {
194 _reg_read(si, SI24_REG_STATUS, &flags, 1);
197 if (flags & (1 << MAX_RT)) {
198 ev.type = EV_ERR_MAX_RETRIES;
205 _reg_write(si, SI24_W_TX_PAYLOAD_NO_ACK, buf + idx, sz);
206 si->ctl->chip_enable(1);
207 while (!(flags & (1 << TX_DS)) && timeout < TIMEOUT) {
208 _reg_read(si, SI24_REG_STATUS, &flags, 1);
213 if (timeout >= TIMEOUT) {
214 ev.type = EV_ERR_TIMEOUT;
220 flags |= (1 << TX_DS);
221 _reg_write(si, SI24_REG_STATUS, &flags, 1);
222 _reg_read(si, SI24_REG_STATUS, &flags, 1);
227 ev.type = EV_TX_COMPLETE;
229 si->ctl->chip_enable(0);
234 size_t si24_recv(si24_t* si, unsigned char * buf, size_t size)
237 size_t bytes_read = 0;
238 uint8_t p_size = si->opts->payload;
239 uint8_t tmpbuf[p_size];
243 if (si->opts->mode == SEND_MODE)
246 _reg_read(si, SI24_REG_STATUS, &flags, 1);
248 if (!(flags & (1 << RX_DR))) {
249 ev.type = EV_RX_EMPTY;
254 /* do not accept any new incoming data */
255 si->opts->ioctl->chip_enable(0);
257 _reg_read(si, SI24_REG_FIFO_SATUS, &fifo_flags, 1);
258 while(!(fifo_flags & (1 << RX_EMPTY)) &&
261 if (si->opts->enable_dynpd) {
263 _reg_read(si, SI24_RX_PL_WID, &d_sz, 1);
266 int m_size = (size - bytes_read) > p_size ? p_size : (size - bytes_read);
267 _reg_read(si, SI24_R_RX_PAYLOAD, tmpbuf, m_size);
269 memcpy(buf + bytes_read, tmpbuf, m_size);
270 bytes_read += m_size;
272 _reg_read(si, SI24_REG_FIFO_SATUS, &fifo_flags, 1);
275 /* only clear data ready flag when FIFO is empty */
276 if (fifo_flags & (1 << RX_EMPTY)) {
277 flags |= (1 << RX_DR);
278 _reg_write(si, SI24_REG_STATUS, &flags, 1);
281 ev.type = EV_RX_COMPLETE;
284 si->opts->ioctl->chip_enable(1);
289 void si24_reset(si24_t* si)
291 if (si->opts->mode == RECV_MODE) {
292 _reg_write(si, SI24_FLUSH_RX, 0, 0);
294 else if (si->opts->mode == SEND_MODE) {
295 _reg_write(si, SI24_FLUSH_TX, 0, 0);
298 uint8_t status_reg = {0};
299 status_reg |= (1 << RX_DR);
300 status_reg |= (1 << TX_DS);
301 status_reg |= (1 << MAX_RT);
303 _reg_write(si, SI24_REG_STATUS, (uint8_t *) &status_reg, 1);
305 si->ctl->chip_enable(0);
308 void si24_free(si24_t * si)