3 * Author : Robin Krens <robin@robinkrens.nl>
5 * Last Modified Date: 22.01.2023
6 * Last Modified By : Robin Krens <robin@robinkrens.nl>
16 #include "libsi24reg.h"
21 const si24_opts_t *opts;
22 const si24_ioctl_t *ctl;
23 si24_event_handler_t eh;
26 static uint8_t _reg_read(si24_t *si, uint8_t reg,
27 uint8_t *data, int sz)
32 buf[0] = reg | SI24_R_REGISTER;
35 if (si->ctl->write_and_read(buf, sz+1) == -1) {
42 memcpy(data, (buf+1), sz);
47 static uint8_t _reg_write(si24_t *si, uint8_t reg,
48 const uint8_t *data, int sz)
52 buf[0] = reg | SI24_W_REGISTER;
53 memcpy((buf+1), data, sz);
56 printf("REG 0x%x:\t", reg);
57 for (int i = 1; i <= sz; ++i) {
58 fprintf(stdout, "0x%x(%c)", buf[i], buf[i]);
60 fprintf(stdout, "\n");
63 if (si->ctl->write_and_read(buf, sz+1) == -1) {
73 static int _config(si24_t * si)
76 uint8_t config_reg = (1 << PWR_UP);
77 uint8_t feature_reg = 0x0; /* default value */
78 uint8_t rf_setup_reg = 0xE; /* default value */
79 uint8_t setup_retr_reg = 0x3; /* default value */
80 const uint8_t rf_ch_reg = 0x40; /* default value */
81 const si24_opts_t * params = si->opts;
83 if (params->enable_crc) {
84 config_reg |= (1 << EN_CRC);
85 config_reg |= (si->opts->crc << CRCO);
88 if (params->enable_ack) {
89 uint8_t dyn = (1 << DPL_P0);
90 ret += _reg_write(si, SI24_REG_DYNPD, &dyn, 1);
91 feature_reg |= (1 << EN_DPL);
92 ret += _reg_write(si, SI24_REG_FEATURE, &feature_reg, 1);
93 if (params->mode == SEND_MODE) {
94 setup_retr_reg = ARD(params->timeout) | ARC(params->retries);
95 ret += _reg_write(si, SI24_REG_SETUP_RETR, &setup_retr_reg, 1);
98 if (params->mode == SEND_MODE) {
99 feature_reg |= (1 << EN_DYN_ACK);
100 ret += _reg_write(si, SI24_REG_FEATURE, &feature_reg, 1);
105 if (params->mac_addr & 0xF0000) {
107 ret += _reg_write(si, SI24_REG_SETUP_AW, &aw, 1);
108 } else if (params->mac_addr & 0xF000) {
110 ret += _reg_write(si, SI24_REG_SETUP_AW, &aw, 1);
113 ret += _reg_write(si, SI24_REG_SETUP_AW, &aw, 1);
119 if (params->mode == SEND_MODE && params->enable_ack) {
120 ret += _reg_write(si, SI24_REG_RX_ADDR_P0, (uint8_t *) ¶ms->mac_addr, aw);
123 if (params->mode == RECV_MODE) {
124 config_reg |= (1 << PRIM_RX);
126 ret += _reg_write(si, SI24_REG_EN_RXADDR, &ch, 1);
127 ret += _reg_write(si, SI24_REG_RX_ADDR_P0, (uint8_t *) ¶ms->mac_addr, aw);
128 ret += _reg_write(si, SI24_REG_RX_PW_P0, (uint8_t *) ¶ms->payload, 1);
130 ret += _reg_write(si, SI24_REG_TX_ADDR, (uint8_t *) ¶ms->mac_addr, aw);
133 rf_setup_reg |= (params->speed << RF_DR_HIGH);
134 rf_setup_reg |= (params->txpwr << RF_PWR);
135 ret += _reg_write(si, SI24_REG_RF_SETUP, &rf_setup_reg, 1);
138 ret += _reg_write(si, SI24_REG_RF_CH, &rf_ch_reg, 1);
139 ret += _reg_write(si, SI24_REG_CONFIG, &config_reg, 1);
141 if (params->mode == RECV_MODE) {
142 /* start accepting data immediately,
143 * for send mode it is onyl activated upon sending */
144 params->ioctl->chip_enable(1);
150 si24_t* si24_init(const si24_opts_t *opts, si24_event_handler_t eh)
152 struct si24_t *si = (si24_t*) calloc(1, sizeof(si24_t));
157 si->ctl = opts->ioctl;
160 int ret = _config(si);
169 size_t si24_send(si24_t* si, const unsigned char * buf, size_t size)
172 uint16_t timeout = 0;
176 if (si->opts->mode == RECV_MODE)
179 _reg_read(si, SI24_REG_STATUS, (uint8_t *) &flags, 1);
181 if (flags & (1 << TX_FULL)) {
182 ev.type = EV_TX_FULL;
187 for (size_t idx = 0; idx < size; idx += si->opts->payload) {
188 sz = (size - idx) < si->opts->payload ? (size - idx) : si->opts->payload;
189 if (si->opts->enable_ack) {
190 _reg_write(si, SI24_W_TX_PAYLOAD, buf + idx, sz);
191 si->ctl->chip_enable(1);
192 while ((!(flags & (1 << TX_DS)) && !(flags & (1 << MAX_RT))) && timeout < 1000) {
193 _reg_read(si, SI24_REG_STATUS, &flags, 1);
196 if (flags & (1 << MAX_RT)) {
197 ev.type = EV_ERR_MAX_RETRIES;
204 _reg_write(si, SI24_W_TX_PAYLOAD_NO_ACK, buf + idx, sz);
205 si->ctl->chip_enable(1);
206 while (!(flags & (1 << TX_DS)) && timeout < 1000) {
207 _reg_read(si, SI24_REG_STATUS, &flags, 1);
212 if (timeout >= 1000) {
213 ev.type = EV_ERR_TIMEOUT;
222 ev.type = EV_TX_COMPLETE;
224 si->ctl->chip_enable(0);
229 size_t si24_recv(si24_t* si, unsigned char * buf, size_t size)
232 size_t bytes_read = 0;
233 uint8_t p_size = si->opts->payload;
234 uint8_t tmpbuf[p_size];
238 if (si->opts->mode == SEND_MODE)
241 _reg_read(si, SI24_REG_STATUS, &flags, 1);
243 if (!(flags & (1 << RX_DR))) {
244 ev.type = EV_RX_EMPTY;
249 /* do not accept any new incoming data */
250 si->opts->ioctl->chip_enable(0);
252 _reg_read(si, SI24_REG_FIFO_SATUS, &fifo_flags, 1);
253 while(!(fifo_flags & (1 << RX_EMPTY)) &&
256 int m_size = (size - bytes_read) > p_size ? p_size : (size - bytes_read);
257 _reg_read(si, SI24_R_RX_PAYLOAD, tmpbuf, m_size);
258 memcpy(buf + bytes_read, tmpbuf, m_size);
259 bytes_read += m_size;
261 ev.type = EV_RX_COMPLETE;
264 _reg_read(si, SI24_REG_FIFO_SATUS, &fifo_flags, 1);
267 flags |= (1 << RX_DR);
268 _reg_write(si, SI24_REG_STATUS, &flags, 1);
270 si->opts->ioctl->chip_enable(1);
275 void si24_reset(si24_t* si)
277 if (si->opts->mode == RECV_MODE) {
278 _reg_write(si, SI24_FLUSH_RX, 0, 0);
280 else if (si->opts->mode == SEND_MODE) {
281 _reg_write(si, SI24_FLUSH_TX, 0, 0);
284 uint8_t status_reg = {0};
285 status_reg |= (1 << RX_DR);
286 status_reg |= (1 << TX_DS);
287 status_reg |= (1 << MAX_RT);
289 _reg_write(si, SI24_REG_STATUS, (uint8_t *) &status_reg, 1);
291 si->ctl->chip_enable(0);
294 void si24_free(si24_t * si)
299 /* hardware linkage */
300 int spi_w_r(unsigned char *data, size_t sz)
303 data[1] = (1 << RX_DR);
307 void ce(unsigned val)
311 void eh(si24_t *si, si24_event_t * e)
315 printf("SENT SUCCESFUL\n");
318 printf("RECV COMPLETE\n");
321 printf("NO NEW DATA\n");
327 printf("EVENT: %x\n", e->type);
334 const unsigned char buf[] = "THIS IS A WIRELESS TEST MESSAGE!";
335 unsigned char recv_buf[29];
338 .write_and_read = spi_w_r,
342 const si24_opts_t opts = {
355 .mac_addr = 0xAAAAAAAAAA
358 struct si24_t * si = si24_init(&opts, eh);
359 /* si24_send(si, buf, sizeof(buf)); */
360 printf("READ: %ld\n", si24_recv(si, recv_buf, sizeof(recv_buf)));