7 /* TIMER, TODO: move to timer.c */
11 /* Interrupt vector can contain 16 exceptions and up to 256 interrupts
12 * In this code we use 16 exceptions and 36 interrupts
13 * (note: this should be aligned to the vector table size)
14 * Offsets of each entry is: 0x0, 0x80, 0x100, 0x180 .. */
16 /* interrupt vector 1-15: processor exceptions
17 * interrupt vector 16-43: irq0 - irq .. */
20 /* * base is location of interrupt service request
22 void ivt_set_gate(unsigned char num, void * isr(), short pri) {
24 ivt[num] = (uint32_t) isr;
28 // test Interrupt service routine
33 /* Initialize interrupt vector */
37 /* clear entiry IVT, in SRAM location for SRAM + .data (in .bss section) */
38 memset(&ivt, 0, (sizeof(uint32_t) * 44));
40 // stack top is loaded from the first entry table on boot/reset
41 // don't need to relocate or init this here
44 extern void * reset, * nmi, * hardfault;
45 //extern uint32_t reset, nmi, hardfault;
48 //ivt[3] = &hardfault;
50 ivt_set_gate(1, test_ISR, 0);
51 ivt_set_gate(2, test_ISR, 0);
52 ivt_set_gate(3, test_ISR, 0);
53 ivt_set_gate(15, test_ISR ,0);
55 // enable all interrupts
57 *SYSCTRL_RCGC1 = *SYSCTRL_RCGC1 | 0x00010000;
61 *NVIC_EN0 = *NVIC_EN0 | 0x00008003;
62 // *NVIC_EN1 = (volatile uint32_t) 0xFFFFFFFF; // TODO not all registers
64 // priority levels are 0 by default (only executable by kernel)
66 /* disable all interrupts
67 * MOV R0, #1 ; disable all
69 * MOV R0, #0 ; allow all
74 /* relocate the vector table to (S)RAM
75 * vector table starts at 0x0. since the address 0x0 point to bootcode, it is on ROM or FLASH.
76 * the value cannot be changed during runtime. however, the vector table can be
77 * relocated to other memory locations in the code or RAM later on
79 * we can do this by setting a register in the NVIC called
80 * the vector table offset register (address 0xE000ED08). */
83 *NVIC_VECTTBL = (volatile unsigned long) &ivt;