1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/7/20 - ROBIN KRENS
8 * Memory map for the Cortex-A3
9 * Implementations vary among manufacturers. This one is
10 * a STM32F013RC6. Addresses of peripherals vary amongst
11 * manufacturers of boards with similar chips
14 * These are volatile memory addresses of 32 bit. The macro's
15 * MEM_VALUE and MEM_ADDR should used.
16 * In case you want to use a address on the lside of a assigment
17 * use volatile uint32_t * p = MEM_ADDR(0x20000000);
25 /* 64kB SRAM located at SRAM_OFFSET */
26 #define SRAM_SIZE 0x00010000
27 #define SRAM_OFFSET 0x20000000
29 /* Safety macro's to get the address or value */
30 #define MEM_VALUE(addr) *((volatile uint32_t(*) (addr))
31 #define MEM_ADDR(addr) ((volatile uint32_t *) (addr))
33 /* SYSTEM INFO AND DEBUG */
34 #define MCU_ID MEM_ADDR(0xE000ED00)
35 #define FLASH_MEM MEM_ADDR(0x1FFFF000)
37 /* SYSTEM CONTROL BLOCK REGISTER */
38 #define SCB_VTOR MEM_ADDR(0xE000ED08) // VECTOR TABLE
39 #define SCB_VTOR_ST MEM_ADDR(0xE000ED04) // STATUS OF VECTOR
40 #define SCB_CCR MEM_ADDR(0xE000ED14) // SET SOFTWARE TRAPS
42 /* NESTED VECTOR INTERRUPT CONTROL REGISTER */
43 #define NVIC_ISER0 MEM_ADDR(0xE000E100) // interrupt set enable register
44 #define NVIC_ISER1 MEM_ADDR(0xE000E104) // interrupt set enable register
46 /* SYSTICK REGISTER */
47 #define STK_CTRL MEM_ADDR(0xE000E010)
48 #define STK_RELOAD MEM_ADDR(0xE000E014)
51 #define RCC_CR MEM_ADDR(0x40021000)
52 #define RCC_CFGR MEM_ADDR(0x40021004)
54 /* SYSTEM CONTROL REGISTER */
55 #define SYSCTRL_RCC MEM_ADDR(0x40021000)
56 #define RCC_APB1ENR MEM_ADDR(0x4002101C) // register to enable I2C
57 #define RCC_APB2ENR MEM_ADDR(0x40021018) // register to enable USART1
59 #define SYSCTRL_RIS MEM_ADDR(0x400FE050)
60 #define SYSCTRL_RCGC1 MEM_ADDR(0x400FE104)
61 #define SYSCTRL_RCGC2 MEM_ADDR(0x400FE108)
62 #define GPIOPA_AFSEL MEM_ADDR(0x40004420)
64 #define GPIOA_CRH MEM_ADDR(0x40010804) // for USART1
65 #define GPIOB_CRL MEM_ADDR(0x40010C00) // low register (!) for I2C1
66 #define GPIOC_CRL MEM_ADDR(0x40011000) // for led
67 #define GPIOC_ODR MEM_ADDR(0x4001100C) //
69 #define AFIO_EVCR MEM_ADDR(0x40010000)
71 /* EXTERNAL INTERRUPTS */
72 #define EXTI_IMR MEM_ADDR(0x40010400)
73 #define EXTI_RTSR MEM_ADDR(0x40010408)
76 #define USART1_BASE MEM_ADDR(0x40013800)
77 #define USART1_SR MEM_ADDR(0x40013800)
78 #define USART1_DR MEM_ADDR(0x40013804)
79 #define USART1_BRR MEM_ADDR(0x40013808)
80 #define USART1_CR1 MEM_ADDR(0x4001380C)
81 #define USART1_CR2 MEM_ADDR(0x40013810)
82 #define USART1_CR3 MEM_ADDR(0x40013814)