1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/7/20 - ROBIN KRENS
8 * Example memory map for the Cortex-A3
9 * Implementations vary among manufacturers. This one is
10 * a STM32F013RC6. Addresses of peripherals vary amongst
11 * manufacturers of boards with similar chips
14 * These are volatile memory addresses of 32 bit. The macro's
15 * MEM_VALUE and MEM_ADDR should used.
16 * In case you want to use a address on the lside of a assigment
17 * use volatile uint32_t * p = MEM_ADDR(0x20000000);
25 /* Safety macro's to get the address or value */
26 #define MEM_VALUE(addr) *((volatile uint32_t(*) (addr))
27 #define MEM_ADDR(addr) ((volatile uint32_t *) (addr))
29 /* SYSTEM INFO AND DEBUG */
30 #define MCU_ID MEM_ADDR(0xE000ED00)
31 #define FLASH_MEM MEM_ADDR(0x1FFFF000)
33 /* SYSTEM CONTROL BLOCK REGISTER */
34 #define SCB_VTOR MEM_ADDR(0xE000ED08) // VECTOR TABLE
35 #define SCB_VTOR_ST MEM_ADDR(0xE000ED04) // STATUS OF VECTOR
36 #define SCB_CCR MEM_ADDR(0xE000ED14) // SET SOFTWARE TRAPS
38 /* NESTED VECTOR INTERRUPT CONTROL REGISTER */
39 #define NVIC_ISER0 MEM_ADDR(0xE000E100) // interrupt set enable register
40 #define NVIC_ISER1 MEM_ADDR(0xE000E104) // interrupt set enable register
42 /* SYSTICK REGISTER */
43 #define STK_CTRL MEM_ADDR(0xE000E010)
44 #define STK_RELOAD MEM_ADDR(0xE000E014)
47 #define RCC_CR MEM_ADDR(0x40021000)
48 #define RCC_CFGR MEM_ADDR(0x40021004)
50 /* SYSTEM CONTROL REGISTER */
51 #define SYSCTRL_RCC MEM_ADDR(0x40021000)
52 #define RCC_APB2ENR MEM_ADDR(0x40021018) // register to enable USART1
54 #define SYSCTRL_RIS MEM_ADDR(0x400FE050)
55 #define SYSCTRL_RCGC1 MEM_ADDR(0x400FE104)
56 #define SYSCTRL_RCGC2 MEM_ADDR(0x400FE108)
57 #define GPIOPA_AFSEL MEM_ADDR(0x40004420)
59 #define GPIOA_CRH MEM_ADDR(0x40010804)
61 #define AFIO_EVCR MEM_ADDR(0x40010000)
63 /* EXTERNAL INTERRUPTS */
64 #define EXTI_IMR MEM_ADDR(0x40010400)
65 #define EXTI_RTSR MEM_ADDR(0x40010408)
68 #define USART1_BASE MEM_ADDR(0x40013800)
69 #define USART1_SR MEM_ADDR(0x40013800)
70 #define USART1_DR MEM_ADDR(0x40013804)
71 #define USART1_BRR MEM_ADDR(0x40013808)
72 #define USART1_CR1 MEM_ADDR(0x4001380C)
73 #define USART1_CR2 MEM_ADDR(0x40013810)
74 #define USART1_CR3 MEM_ADDR(0x40013814)