1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/8/4 - ROBIN KRENS
18 #include <sys/robsys.h>
20 #include <lib/regfunc.h>
21 #include <lib/string.h>
22 #include <lib/tinyprintf.h>
24 #include <drivers/tsensor.h>
26 #define PRESCALER 36000 // 1 Mhz
28 int *ccr1, *ccr2, *ccr1b, *ccr2b;
31 void * update_handler() {
40 if(rchkbit(TIM4_SR1, 1)) {
42 // printf("CCR1: %p\n", *TIM4_CCR1);
43 // printf("CCR2: %p\n", *TIM4_CCR2);
49 if(rchkbit(TIM4_SR1, 2)) {
56 if(rchkbit(TIM4_SR1, 6)) {
57 // printf("TRIGGER\n");
62 // rclrbit(TIM4_SR1, 9); // OF
63 // rclrbit(TIM4_SR1, 10); // OF
65 // TODO clear overflow tag
67 printf("SR1/CCR1: %p\n", ccr1);
68 printf("SR1/CCR2: %p\n", ccr2);
69 printf("SR2/CCR1: %p\n", ccr1b);
70 printf("SR2/CCR2: %p\n", ccr2b);
73 printf("EDGE DOWN\n");
82 rwrite(GPIOB_CRL, 0x44444444);
85 void * tmp_update_handler() {
87 printf("SR: %p\n", *TIM4_SR1);
89 rclrbit(TIM4_CR1, 0); /* EMULATOR STOP */
93 tsensor_input(0xFFFF);
95 // if(rchkbit(TIM4_SR1, 1)) {
101 void * cnt_complete_handler() {
102 rclrbit(TIM4_CR1, 0);
103 rclrbit(TIM4_SR1, 0);
104 rclrbit(TIM4_DIER, 0);
105 rwrite(GPIOB_CRL, 0x44444444);
106 printf("CNT COMPLETE\n");
107 tsensor_input(0xFFFF);
111 void tsensor_simple(uint16_t preload) {
113 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
115 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
116 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
117 rsetbit(TIM4_CR1, 2); // only overflow generates update
119 rwrite(TIM4_PSC, PRESCALER - 1);
120 rwrite(TIM4_ARR, preload);
121 rsetbit(TIM4_EGR, 0);
123 ivt_set_gate(46, cnt_complete_handler, 0);
124 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
126 rsetbit(GPIOB_BSRR, 22); //
127 rsetbit(TIM4_DIER, 0);
128 rsetbit(TIM4_CR1, 0);
134 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
135 rwrite(GPIOB_CRL, 0x47444444); // open drain general
137 rsetbit(GPIOB_BSRR, 22); // high
138 tsensor_simple(2000);
139 // tsensor_output(580, 520);
141 // tsensor_simple(580);
144 void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
147 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
148 rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
149 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
151 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
152 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
153 rsetbit(TIM4_CR1, 2); // only overflow generates update
155 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
156 rwrite(TIM4_ARR, preload); // preload
157 rwrite(TIM4_CCR1, compare); // compare
158 //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
160 rsetbit(TIM4_EGR, 0); // update generation
162 rsetbit(TIM4_CR1, 3); // one pulse mode
163 rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
165 //rsetbit(TIM4_CCMR1, 3); // preload enable
166 //rsetbit(TIM4_CR1, 7); // buffered
168 rsetbit(TIM4_CCER, 0); // enable output channeli 1
169 rsetbit(TIM4_CCER, 1); // active low
170 rsetbit(TIM4_CR1, 0); // start counter
173 ivt_set_gate(46, tmp_update_handler, 0);
175 rsetbit(TIM4_DIER, 1);
176 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
180 void tsensor_input(uint16_t preload) {
182 //uint16_t timestamp;
184 //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
185 //rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
186 //rsetbit(RCC_APB1ENR, 2); // TIM4 enable
188 //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
189 //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
191 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
192 rwrite(TIM4_ARR, preload); // preload
195 rsetbit(TIM4_EGR, 0); // update generation
197 rsetbit(TIM4_CCMR1, 0); // input on TI1
198 rsetbit(TIM4_CCMR1, 9); // another input TI2
199 rsetbit(TIM4_CCER, 1); // other polarity for T1, inverted
201 /* TODO: reg funct */
202 rsetbit(TIM4_SMCR, 4); // OLD: 101, new Edge detector
203 rsetbit(TIM4_SMCR, 6); //
206 // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
207 rsetbit(TIM4_SMCR, 2); // OLD: 110
208 rsetbit(TIM4_SMCR, 1);
209 rsetbit(TIM4_SMCR, 0);
210 //rsetbit(TIM4_SMCR, 1); // 110
212 //rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
213 // will catch multiple signal... can set fram
215 rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
216 rsetbit(TIM4_CCER, 4); // enable capture channel 2
217 /* Caught on rising edge, no need to change*/
218 /* Clear capture event flag */
219 // rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
221 // enable capture channel 1 interrupt
222 rsetbit(TIM4_DIER, 1);
223 rsetbit(TIM4_DIER, 2);
224 ivt_set_gate(46, update_handler, 0);
225 rsetbit(NVIC_ISER0, 30);