1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/8/4 - ROBIN KRENS
18 #include <sys/robsys.h>
20 #include <lib/regfunc.h>
21 #include <lib/string.h>
22 #include <lib/tinyprintf.h>
24 #include <drivers/tsensor.h>
26 #define PRESCALER 8000 // 1 kHz
28 int *ccr1, *ccr2, *ccr1b, *ccr2b;
31 void * update_handler() {
40 if(rchkbit(TIM4_SR1, 1)) {
42 // printf("CCR1: %p\n", *TIM4_CCR1);
43 // printf("CCR2: %p\n", *TIM4_CCR2);
49 if(rchkbit(TIM4_SR1, 2)) {
56 if(rchkbit(TIM4_SR1, 6)) {
57 // printf("TRIGGER\n");
62 // rclrbit(TIM4_SR1, 9); // OF
63 // rclrbit(TIM4_SR1, 10); // OF
65 // TODO clear overflow tag
67 printf("SR1/CCR1: %p\n", ccr1);
68 printf("SR1/CCR2: %p\n", ccr2);
69 printf("SR2/CCR1: %p\n", ccr1b);
70 printf("SR2/CCR2: %p\n", ccr2b);
73 printf("EDGE DOWN\n");
82 rwrite(GPIOB_CRL, 0x44444444);
85 void * tmp_update_handler() {
87 printf("SR: %p\n", *TIM4_SR1);
89 rclrbit(TIM4_CR1, 0); /* EMULATOR STOP */
93 tsensor_input(0xFFFF);
95 // if(rchkbit(TIM4_SR1, 1)) {
101 void * cnt_complete_handler() {
102 rclrbit(TIM4_CR1, 0);
103 rclrbit(TIM4_SR1, 0);
104 rclrbit(TIM4_DIER, 0);
105 rwrite(GPIOB_CRL, 0x44444444);
106 printf("CNT COMPLETE\n");
107 tsensor_input(0xFFFF);
112 void * bare_handler() {
115 //w2 printf("CHECKING STATUS\n");
117 //w2 if(rchkbit(GPIOB_IDR, 6)) {
118 //w2 printf("port high\n");
121 //w2 printf("port low\n");
126 printf("Count event %d\n", cnt);
127 int switchled = cnt % 2;
129 printf("setting low\n");
130 rclrbit(GPIOB_ODR, 6); // low
133 printf("setting high\n");
134 rsetbit(GPIOB_ODR, 6); // high
136 rclrbit(TIM4_SR1, 0);
140 void tsensor_simple(uint16_t preload) {
142 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
144 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
145 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
146 rsetbit(TIM4_CR1, 2); // only overflow generates update
148 rwrite(TIM4_PSC, PRESCALER - 1);
149 rwrite(TIM4_ARR, preload);
150 rsetbit(TIM4_EGR, 0);
152 ivt_set_gate(46, bare_handler, 0);
153 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
155 //w rsetbit(GPIOB_ODR, 6); //
156 rsetbit(TIM4_DIER, 0);
157 rsetbit(TIM4_CR1, 0);
164 //w2 rsetbit(RCC_APB2ENR, 3);
165 //w2 rwrite(GPIOB_CRL, 0x48444444); // input with pull up down
166 //w2 tsensor_simple(5000);
169 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
170 rwrite(GPIOB_CRL, 0x46444444); // open drain general for sensor?
172 rsetbit(GPIOB_BSRR, 22); // low (<- reset)
174 tsensor_simple(4000); // 2 second?
176 // tsensor_output(580, 520);
178 // tsensor_simple(580);
181 void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
184 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
185 rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
186 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
188 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
189 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
190 rsetbit(TIM4_CR1, 2); // only overflow generates update
192 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
193 rwrite(TIM4_ARR, preload); // preload
194 rwrite(TIM4_CCR1, compare); // compare
195 //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
197 rsetbit(TIM4_EGR, 0); // update generation
199 rsetbit(TIM4_CR1, 3); // one pulse mode
200 rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
202 //rsetbit(TIM4_CCMR1, 3); // preload enable
203 //rsetbit(TIM4_CR1, 7); // buffered
205 rsetbit(TIM4_CCER, 0); // enable output channeli 1
206 rsetbit(TIM4_CCER, 1); // active low
207 rsetbit(TIM4_CR1, 0); // start counter
210 ivt_set_gate(46, tmp_update_handler, 0);
212 rsetbit(TIM4_DIER, 1);
213 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
217 void tsensor_input(uint16_t preload) {
219 //uint16_t timestamp;
221 //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
222 //rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
223 //rsetbit(RCC_APB1ENR, 2); // TIM4 enable
225 //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
226 //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
228 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
229 rwrite(TIM4_ARR, preload); // preload
232 rsetbit(TIM4_EGR, 0); // update generation
234 rsetbit(TIM4_CCMR1, 0); // input on TI1
235 rsetbit(TIM4_CCMR1, 9); // another input TI2
236 rsetbit(TIM4_CCER, 1); // other polarity for T1, inverted
238 /* TODO: reg funct */
239 rsetbit(TIM4_SMCR, 4); // OLD: 101, new Edge detector
240 rsetbit(TIM4_SMCR, 6); //
243 // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
244 rsetbit(TIM4_SMCR, 2); // OLD: 110
245 rsetbit(TIM4_SMCR, 1);
246 rsetbit(TIM4_SMCR, 0);
247 //rsetbit(TIM4_SMCR, 1); // 110
249 //rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
250 // will catch multiple signal... can set fram
252 rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
253 rsetbit(TIM4_CCER, 4); // enable capture channel 2
254 /* Caught on rising edge, no need to change*/
255 /* Clear capture event flag */
256 // rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
258 // enable capture channel 1 interrupt
259 rsetbit(TIM4_DIER, 1);
260 rsetbit(TIM4_DIER, 2);
261 ivt_set_gate(46, update_handler, 0);
262 rsetbit(NVIC_ISER0, 30);