1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/8/4 - ROBIN KRENS
17 #include <sys/robsys.h>
19 #include <lib/regfunc.h>
20 #include <lib/string.h>
21 #include <lib/tinyprintf.h>
23 #include <drivers/tsensor.h>
25 #define PRESCALER 36000 // 1 Mhz
27 int *ccr1, *ccr2, *ccr1b, *ccr2b;
30 void * update_handler() {
39 if(rchkbit(TIM4_SR1, 1)) {
41 // printf("CCR1: %p\n", *TIM4_CCR1);
42 // printf("CCR2: %p\n", *TIM4_CCR2);
48 if(rchkbit(TIM4_SR1, 2)) {
55 if(rchkbit(TIM4_SR1, 6)) {
56 // printf("TRIGGER\n");
61 // rclrbit(TIM4_SR1, 9); // OF
62 // rclrbit(TIM4_SR1, 10); // OF
64 // TODO clear overflow tag
66 printf("SR1/CCR1: %p\n", ccr1);
67 printf("SR1/CCR2: %p\n", ccr2);
68 printf("SR2/CCR1: %p\n", ccr1b);
69 printf("SR2/CCR2: %p\n", ccr2b);
72 printf("EDGE DOWN\n");
81 rwrite(GPIOB_CRL, 0x44444444);
84 void * tmp_update_handler() {
86 printf("SR: %p\n", *TIM4_SR1);
88 rclrbit(TIM4_CR1, 0); /* EMULATOR STOP */
92 tsensor_input(0xFFFF);
94 // if(rchkbit(TIM4_SR1, 1)) {
100 void * cnt_complete_handler() {
101 rclrbit(TIM4_CR1, 0);
102 rclrbit(TIM4_SR1, 0);
103 rclrbit(TIM4_DIER, 0);
104 rwrite(GPIOB_CRL, 0x44444444);
105 printf("CNT COMPLETE\n");
106 tsensor_input(0xFFFF);
110 void tsensor_simple(uint16_t preload) {
112 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
114 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
115 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
116 rsetbit(TIM4_CR1, 2); // only overflow generates update
118 rwrite(TIM4_PSC, PRESCALER - 1);
119 rwrite(TIM4_ARR, preload);
120 rsetbit(TIM4_EGR, 0);
122 ivt_set_gate(46, cnt_complete_handler, 0);
123 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
125 rsetbit(GPIOB_BSRR, 22); //
126 rsetbit(TIM4_DIER, 0);
127 rsetbit(TIM4_CR1, 0);
133 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
134 rwrite(GPIOB_CRL, 0x47444444); // open drain general
136 rsetbit(GPIOB_BSRR, 22); // high
137 tsensor_simple(2000);
138 // tsensor_output(580, 520);
140 // tsensor_simple(580);
143 void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
146 rsetbit(RCC_APB2ENR, 3); // GPIOB enable
147 rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
148 rsetbit(RCC_APB1ENR, 2); // TIM4 enable
150 rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
151 rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
152 rsetbit(TIM4_CR1, 2); // only overflow generates update
154 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
155 rwrite(TIM4_ARR, preload); // preload
156 rwrite(TIM4_CCR1, compare); // compare
157 //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
159 rsetbit(TIM4_EGR, 0); // update generation
161 rsetbit(TIM4_CR1, 3); // one pulse mode
162 rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
164 //rsetbit(TIM4_CCMR1, 3); // preload enable
165 //rsetbit(TIM4_CR1, 7); // buffered
167 rsetbit(TIM4_CCER, 0); // enable output channeli 1
168 rsetbit(TIM4_CCER, 1); // active low
169 rsetbit(TIM4_CR1, 0); // start counter
172 ivt_set_gate(46, tmp_update_handler, 0);
174 rsetbit(TIM4_DIER, 1);
175 rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
179 void tsensor_input(uint16_t preload) {
181 //uint16_t timestamp;
183 //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
184 //rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
185 //rsetbit(RCC_APB1ENR, 2); // TIM4 enable
187 //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
188 //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
190 rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
191 rwrite(TIM4_ARR, preload); // preload
194 rsetbit(TIM4_EGR, 0); // update generation
196 rsetbit(TIM4_CCMR1, 0); // input on TI1
197 rsetbit(TIM4_CCMR1, 9); // another input TI2
198 rsetbit(TIM4_CCER, 1); // other polarity for T1, inverted
200 /* TODO: reg funct */
201 rsetbit(TIM4_SMCR, 4); // OLD: 101, new Edge detector
202 rsetbit(TIM4_SMCR, 6); //
205 // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
206 rsetbit(TIM4_SMCR, 2); // OLD: 110
207 rsetbit(TIM4_SMCR, 1);
208 rsetbit(TIM4_SMCR, 0);
209 //rsetbit(TIM4_SMCR, 1); // 110
211 //rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
212 // will catch multiple signal... can set fram
214 rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
215 rsetbit(TIM4_CCER, 4); // enable capture channel 2
216 /* Caught on rising edge, no need to change*/
217 /* Clear capture event flag */
218 // rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
220 // enable capture channel 1 interrupt
221 rsetbit(TIM4_DIER, 1);
222 rsetbit(TIM4_DIER, 2);
223 ivt_set_gate(46, update_handler, 0);
224 rsetbit(NVIC_ISER0, 30);