robinkrens.nl - git repository - cortex-from-scratch/blob - drivers/tsensor.c

   1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
   2  *
   3  * $LOG$
   4  * 2019/8/4 - ROBIN KRENS
   5  * PreInitial version
   6  *
   7  * $DESCRIPTION$
   8  * Temperature sensor
   9  * [in dev]
  10  *
  11  * */
  12
  13 #include <stdbool.h>
  14 #include <stddef.h>
  15 #include <stdint.h>
  16
  17 #include <sys/mmap.h>
  18 #include <sys/robsys.h>
  19
  20 #include <lib/regfunc.h>
  21 #include <lib/string.h>
  22 #include <lib/tinyprintf.h>
  23
  24 #include <drivers/tsensor.h>
  25
  26 #define PRESCALER 8000 // 1 kHz
  27
  28 int *ccr1, *ccr2, *ccr1b, *ccr2b;
  29 bool s1, s2;
  30
  31  void * update_handler() {
  32
  33 /*      s1 = false;
  34         s2 = false;
  35         ccr1 = 0xFFFFFFFF;
  36         ccr2 = 0xFFFFFFFF;
  37         ccr1b = 0xFFFFFFFF;
  38         ccr2b = 0xFFFFFFFF;
  39
  40         if(rchkbit(TIM4_SR1, 1)) {
  41                         s1 = true;
  42                 //      printf("CCR1: %p\n", *TIM4_CCR1);
  43                 //      printf("CCR2: %p\n", *TIM4_CCR2);
  44                         ccr1 = *TIM4_CCR1;
  45                         ccr2 = *TIM4_CCR2;
  46                         rclrbit(TIM4_SR1, 1);
  47         }
  48
  49         if(rchkbit(TIM4_SR1, 2)) {
  50                         s2 = true;
  51                         ccr1b = *TIM4_CCR1;
  52                         ccr2b = *TIM4_CCR2;
  53                         rclrbit(TIM4_SR1, 2);
  54         }
  55
  56         if(rchkbit(TIM4_SR1, 6)) {
  57         //              printf("TRIGGER\n");
  58                         rclrbit(TIM4_SR1, 6);
  59         }
  60
  61         rclrbit(TIM4_SR1, 0);
  62 //      rclrbit(TIM4_SR1, 9); // OF
  63 //      rclrbit(TIM4_SR1, 10); // OF
  64
  65         // TODO clear overflow tag
  66
  67         printf("SR1/CCR1: %p\n", ccr1);
  68         printf("SR1/CCR2: %p\n", ccr2);
  69         printf("SR2/CCR1: %p\n", ccr1b);
  70         printf("SR2/CCR2: %p\n", ccr2b);
  71
  72         if (s1)
  73                 printf("EDGE DOWN\n");
  74         if (s2)
  75                 printf("EDGE UP\n");
  76
  77         s1 = false;
  78         s2 = false; */
  79 }
  80
  81 static void reset() {
  82         rwrite(GPIOB_CRL, 0x44444444);
  83 }
  84
  85 void * tmp_update_handler() {
  86
  87         printf("SR: %p\n", *TIM4_SR1);
  88
  89         rclrbit(TIM4_CR1, 0);   /* EMULATOR STOP */
  90         rclrbit(TIM4_SR1, 0);
  91         rclrbit(TIM4_SR1, 1);
  92                 reset();
  93                 tsensor_input(0xFFFF);
  94
  95 //      if(rchkbit(TIM4_SR1, 1)) {
  96 //              printf("TEST\n");
  97 //      }
  98
  99 }
 100
 101 void * cnt_complete_handler() {
 102         rclrbit(TIM4_CR1, 0);
 103         rclrbit(TIM4_SR1, 0);
 104         rclrbit(TIM4_DIER, 0);
 105         rwrite(GPIOB_CRL, 0x44444444);
 106         printf("CNT COMPLETE\n");
 107         tsensor_input(0xFFFF);
 108 }
 109
 110 int cnt;
 111
 112 void * bare_handler() {
 113         cnt += 1;
 114         printf("Count event %d\n", cnt);
 115         int switchled = cnt % 2;
 116         if (switchled) {
 117                 printf("setting low\n");
 118                 rclrbit(GPIOB_ODR, 6); // low
 119         }
 120         else {
 121                 printf("setting high\n");
 122                 rsetbit(GPIOB_ODR, 6); // high
 123         }
 124         rclrbit(TIM4_SR1, 0);
 125 }
 126
 127
 128 void tsensor_simple(uint16_t preload) {
 129
 130         rsetbit(RCC_APB1ENR, 2); // TIM4 enable
 131
 132         rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
 133         rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
 134         rsetbit(TIM4_CR1, 2); // only overflow generates update
 135
 136         rwrite(TIM4_PSC, PRESCALER - 1);
 137         rwrite(TIM4_ARR, preload);
 138         rsetbit(TIM4_EGR, 0);
 139
 140         ivt_set_gate(46, bare_handler, 0);
 141         rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
 142
 143         rsetbit(GPIOB_ODR, 6); //
 144         rsetbit(TIM4_DIER, 0);
 145         rsetbit(TIM4_CR1, 0);
 146
 147 }
 148
 149 void run() {
 150
 151         cnt = 0;
 152         rsetbit(RCC_APB2ENR, 3); // GPIOB enable
 153         rwrite(GPIOB_CRL, 0x42444444); //  open drain general for sensor?
 154
 155         rsetbit(GPIOB_BSRR, 22); // high
 156
 157         tsensor_simple(4000); // 2 second?
 158
 159 //      tsensor_output(580, 520);
 160 //      reset();
 161 //      tsensor_simple(580);
 162 }
 163
 164 void tsensor_output(uint16_t preload, uint16_t compare/*, uint16_t pulses */) {
 165
 166         /* GPIO AND CLOCK */
 167         rsetbit(RCC_APB2ENR, 3); // GPIOB enable
 168         rwrite(GPIOB_CRL, 0x4A444444); // PB6 for Channel 1 TIM4 alternate
 169         rsetbit(RCC_APB1ENR, 2); // TIM4 enable
 170
 171         rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
 172         rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
 173         rsetbit(TIM4_CR1, 2); // only overflow generates update
 174
 175         rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
 176         rwrite(TIM4_ARR, preload); // preload
 177         rwrite(TIM4_CCR1, compare); // compare
 178         //rwrite(TIM4_RCR, pulses - 1); /* repeat ONLY IN ADVANCED TIMER */
 179
 180         rsetbit(TIM4_EGR, 0); // update generation
 181
 182         rsetbit(TIM4_CR1, 3); // one pulse mode
 183         rsetbitsfrom(TIM4_CCMR1, 4, 0x6); // mode
 184
 185         //rsetbit(TIM4_CCMR1, 3); // preload enable
 186         //rsetbit(TIM4_CR1, 7); // buffered
 187
 188         rsetbit(TIM4_CCER, 0); // enable output channeli 1
 189         rsetbit(TIM4_CCER, 1); // active low
 190         rsetbit(TIM4_CR1, 0); // start counter
 191
 192         /* INTERRUPTS */
 193         ivt_set_gate(46, tmp_update_handler, 0);
 194
 195         rsetbit(TIM4_DIER, 1);
 196         rsetbit(NVIC_ISER0, 30); // interupt 41 - 32
 197
 198 }
 199
 200 void tsensor_input(uint16_t preload) {
 201
 202         //uint16_t timestamp;
 203         /* GPIO AND CLOCK */
 204         //rsetbit(RCC_APB2ENR, 3); // GPIOB enable
 205         //rwrite(GPIOB_CRL, 0x44444444); // Input floating (default state)
 206         //rsetbit(RCC_APB1ENR, 2); // TIM4 enable
 207
 208         //rsetbitsfrom(TIM4_CR1, 5, 0x00); // edge-aligned mode
 209         //rclrbit(TIM4_CR1, 4); // upcounter (clrbit! not needed to set)
 210
 211         rwrite(TIM4_PSC, PRESCALER - 1); // 1 MHz
 212         rwrite(TIM4_ARR, preload); // preload
 213
 214
 215         rsetbit(TIM4_EGR, 0); // update generation
 216
 217         rsetbit(TIM4_CCMR1, 0); // input on TI1
 218         rsetbit(TIM4_CCMR1, 9); // another input TI2
 219         rsetbit(TIM4_CCER, 1); // other polarity for T1, inverted
 220
 221         /* TODO: reg funct */
 222         rsetbit(TIM4_SMCR, 4); // OLD: 101, new Edge detector
 223         rsetbit(TIM4_SMCR, 6); //
 224
 225
 226         // rsetbit(TIM4_SMCR, 2); // RESET rising edge triggers counter and generates update
 227         rsetbit(TIM4_SMCR, 2); // OLD: 110
 228         rsetbit(TIM4_SMCR, 1);
 229         rsetbit(TIM4_SMCR, 0);
 230         //rsetbit(TIM4_SMCR, 1); // 110
 231
 232         //rsetbit(TIM4_CR1, 3); // one pulse mode // NOTE: RESET after finised preload
 233         // will catch multiple signal... can set fram
 234
 235         rsetbit(TIM4_CCER, 0); // enable capture channel 1 (changed pos)
 236         rsetbit(TIM4_CCER, 4); // enable capture channel 2
 237         /* Caught on rising edge, no need to change*/
 238         /* Clear capture event flag */
 239 //      rsetbit(TIM4_CR1, 0); // RESET with no trigger mode start
 240
 241         // enable capture channel 1 interrupt
 242         rsetbit(TIM4_DIER, 1);
 243         rsetbit(TIM4_DIER, 2);
 244         ivt_set_gate(46, update_handler, 0);
 245         rsetbit(NVIC_ISER0, 30);
 246
 247 }