1 /* (CC-BY-NC-SA) ROBIN KRENS - ROBIN @ ROBINKRENS.NL
4 * 2019/7/30 - ROBIN KRENS
8 * Routines to setup the high speed external (HSE) clock.
9 * Initially a (less accurate) high speed internal (HSI)
10 * clock is used. PPL is enabled; HSE is input for PPL.
11 * PPL is multiplied to get the desired clock speed.
13 * Some buses might not support the maximum speed and
14 * should be prescaled (i.e. low speed APB)
17 * Check external crystals on board and maximum speed
18 * for buses. In this example, a 8 Mhz external crystal
19 * is used. CPU speed is 36 Mhz. No prescaling is done.
27 #include <sys/robsys.h>
30 #include <lib/regfunc.h>
32 static void setup_hse() {
34 rsetbit(RCC_CR, 16); /* HSE enable */
35 rsetbit(RCC_CFGR, 17); /* HSE divider for PLL entry */
37 while(!rchkbit(RCC_CR, 17)); /* Wait for HSE to come up */
39 rsetbitsfrom(RCC_CFGR, 18, 0x7); /* PLL Multiplayer (x9) */
40 rsetbit(RCC_CFGR, 16); /* HSE as PPL clock source */
41 rsetbit(RCC_CR, 24); /* PLL enable */
42 //rsetbitsfrom(RCC_CFGR, 8, 0x4); /* APB low speed prescraler */
43 rsetbitsfrom(RCC_CFGR, 0, 0x2); /* use PPL as system clock */
45 while(!rchkbit(RCC_CFGR, 3)); /* Wait for the clock switch to complete */