basic heap implementation

[cortex-from-scratch] / include / sys / mmap.h

diff --git a/include/sys/mmap.h b/include/sys/mmap.h
index 4fd043d..4ed901d 100644 (file)
--- a/include/sys/mmap.h
+++ b/include/sys/mmap.h
@@ -5,7 +5,7 @@
  * Initial version 
  * 
  * $DESCRIPTION$
- * Memory map for the Cortex-A3
+ * Memory map for the Cortex-M3
  * Implementations vary among manufacturers. This one is
  * a STM32F013RC6. Addresses of peripherals vary amongst 
  * manufacturers of boards with similar chips
@@ -26,13 +26,18 @@
 #define SRAM_SIZE      0x00010000 
 #define SRAM_OFFSET    0x20000000
 
+/* TODO #define KHEAP_SIZE     0x100 */
+
 /* Safety macro's to get the address or value */
 #define MEM_VALUE(addr) *((volatile uint32_t(*) (addr))
 #define MEM_ADDR(addr) ((volatile uint32_t *) (addr))
 
 /* SYSTEM INFO AND DEBUG */
 #define MCU_ID MEM_ADDR(0xE000ED00) 
-#define FLASH_MEM MEM_ADDR(0x1FFFF000) 
+#define FLASH_MEM MEM_ADDR(0x1FFFF000)
+
+/* POWER CONTROL REGISTERS */
+#define PWR_CR MEM_ADDR(0x40007000)
 
 /* SYSTEM CONTROL BLOCK REGISTER */
 #define SCB_VTOR MEM_ADDR(0xE000ED08) // VECTOR TABLE
@@ -42,18 +47,23 @@
 /* NESTED VECTOR INTERRUPT CONTROL REGISTER */
 #define NVIC_ISER0 MEM_ADDR(0xE000E100) // interrupt set enable register
 #define NVIC_ISER1 MEM_ADDR(0xE000E104) // interrupt set enable register
+#define NVIC_ISER2 MEM_ADDR(0xE000E108) // interrupt set enable register
 
 /* SYSTICK REGISTER */
 #define STK_CTRL MEM_ADDR(0xE000E010)
 #define STK_RELOAD MEM_ADDR(0xE000E014)
+#define STK_CALIB MEM_ADDR(0xE000E01C)
 
-/* CLOCK REGISTER */
+/* RESET AND CLOCK REGISTER */
 #define RCC_CR MEM_ADDR(0x40021000)
 #define RCC_CFGR MEM_ADDR(0x40021004)
+#define RCC_BDCR MEM_ADDR(0x40021020)
 
 /* SYSTEM CONTROL REGISTER */
 #define SYSCTRL_RCC MEM_ADDR(0x40021000)
+#define RCC_AHBENR MEM_ADDR(0x40021014) // enable DMA1
 #define RCC_APB1ENR MEM_ADDR(0x4002101C) // register to enable I2C
+#define RCC_APB1RSTR MEM_ADDR(0x40021010) // register to reset I2C
 #define RCC_APB2ENR MEM_ADDR(0x40021018) // register to enable USART1
 
 #define SYSCTRL_RIS MEM_ADDR(0x400FE050)
@@ -62,13 +72,23 @@
 #define GPIOPA_AFSEL MEM_ADDR(0x40004420)
 
 #define GPIOA_CRH MEM_ADDR(0x40010804) // for USART1
+#define GPIOA_CRL MEM_ADDR(0x40010800) // for ADC1
+#define GPIOA_ODR MEM_ADDR(0x4001080C)
 #define GPIOB_CRL MEM_ADDR(0x40010C00) // low register (!) for I2C1
-#define GPIOC_CRL MEM_ADDR(0x40011000) // for led
-#define GPIOC_ODR MEM_ADDR(0x4001100C) //
+#define GPIOB_CRH MEM_ADDR(0x40010C04) // high register for SPI2
+#define GPIOB_BSRR MEM_ADDR(0x40010C10)
+#define GPIOB_ODR MEM_ADDR(0x40010C0C)
+#define GPIOB_IDR MEM_ADDR(0x40010C08)
+#define GPIOC_CRL MEM_ADDR(0x40011000) // SPI2 uses D/CX (A0) 
+#define GPIOC_CRH MEM_ADDR(0x40011004) 
+#define GPIOC_ODR MEM_ADDR(0x4001100C)
+
+#define GPIOD_CRL MEM_ADDR(0x40011400)
+#define GPIOD_ODR MEM_ADDR(0x4001140C)
 
 #define AFIO_EVCR MEM_ADDR(0x40010000)
 
-/* I2C REGISTER */
+/* I2C REGISTERS */
 #define I2C_CR1 MEM_ADDR(0x40005400)
 #define I2C_CR2 MEM_ADDR(0x40005404)
 #define I2C_DR MEM_ADDR(0x40005410)
@@ -77,6 +97,14 @@
 #define I2C_CCR MEM_ADDR(0x4000541C)
 #define I2C_TRISE MEM_ADDR(0x40005420)
 
+/* SPI2 REGISTERS */
+#define SPI2_CR1 MEM_ADDR(0x40003800)
+#define SPI2_CR2 MEM_ADDR(0x40003804)
+#define SPI2_SR MEM_ADDR(0x40003808)
+#define SPI2_DR MEM_ADDR(0x4000380C)
+#define SPI2_CFGR MEM_ADDR(0x4000381C)
+#define SPI2_PR MEM_ADDR(0x40003820)
+
 /* EXTERNAL INTERRUPTS */
 #define EXTI_IMR MEM_ADDR(0x40010400)
 #define EXTI_RTSR MEM_ADDR(0x40010408)
@@ -89,3 +117,49 @@
 #define USART1_CR1 MEM_ADDR(0x4001380C)
 #define USART1_CR2 MEM_ADDR(0x40013810)
 #define USART1_CR3 MEM_ADDR(0x40013814)
+
+/* REAL TIME CLOCK REGISTERS */
+#define RTC_CRH MEM_ADDR(0x40002800) // interrupts
+#define RTC_CRL MEM_ADDR(0x40002804)
+#define RTC_PRLL MEM_ADDR(0x4000280C)
+#define RTC_CNTH MEM_ADDR(0x40002818)
+#define RTC_CNTL MEM_ADDR(0x4000281C)
+/* BACKUP (CALIBR) REGISTERS */
+#define BKP_RTCCR MEM_ADDR(0x40006C2C) // RTC Calibration 
+
+/* TIMERS */
+#define TIM4_CR1 MEM_ADDR(0x40000800)
+#define TIM4_RCR MEM_ADDR(0x40000830)
+#define TIM4_ARR MEM_ADDR(0x4000082C)
+#define TIM4_EGR MEM_ADDR(0x40000814)
+#define TIM4_SR1 MEM_ADDR(0x40000810)
+#define TIM4_CCR1 MEM_ADDR(0x40000834)
+#define TIM4_CCR2 MEM_ADDR(0x40000838)
+#define TIM4_PSC MEM_ADDR(0x40000828)
+#define TIM4_SMCR MEM_ADDR(0x40000808)
+#define TIM4_CCER MEM_ADDR(0x40000820)
+//#define TIM1_BDTR MEM_ADDR(0x40000844)
+#define TIM4_CCMR1 MEM_ADDR(0x40000818)
+#define TIM4_DIER MEM_ADDR(0x4000080C)
+
+/* ANALOG TO DIGITAL CONVERSION 
+ * (ADC1) */
+#define ADC1_SR1 MEM_ADDR(0x40012400)
+#define ADC1_CR1 MEM_ADDR(0x40012404)
+#define ADC1_CR2 MEM_ADDR(0x40012408)
+#define ADC1_SMPR2 MEM_ADDR(0x40012410)
+#define ADC1_HTR MEM_ADDR(0x40012424)
+#define ADC1_LTR MEM_ADDR(0x40012428)
+#define ADC1_SQR1 MEM_ADDR(0x4001242C)
+#define ADC1_SQR3 MEM_ADDR(0x40012434)
+#define ADC1_DR MEM_ADDR(0x4001244C)
+
+/* DMA1 Channel 1 */
+#define DMA_IFCR MEM_ADDR(0x40020004)
+#define DMA_CCR1 MEM_ADDR(0x40020008)
+#define DMA_CPAR1 MEM_ADDR(0x40020010)
+#define DMA_CMAR1 MEM_ADDR(0x40020014)
+#define DMA_CNDTR1 MEM_ADDR(0x4002000C)
+
+
+