--- /dev/null
+;--------------------------------------------\r
+; Wonderswan Registers & Equates v0.2\r
+; by Orion_ [2008]\r
+;\r
+; http://onorisoft.free.fr/\r
+;\r
+; with help of WStech24.txt by Judge and Dox\r
+;--------------------------------------------\r
+\r
+; IO_ mean byte access\r
+; IOw_ mean word access\r
+\r
+\r
+;-------------\r
+; Rom Header\r
+\r
+RH_ROM_4MBITS equ 0x02\r
+RH_ROM_8MBITS equ 0x03\r
+RH_ROM_16MBITS equ 0x04\r
+RH_ROM_32MBITS equ 0x06\r
+RH_ROM_64MBITS equ 0x08\r
+RH_ROM_128MBITS equ 0x09\r
+\r
+RH_NO_SRAM equ 0x00\r
+RH_SRAM_64KBITS equ 0x01\r
+RH_SRAM_256KBITS equ 0x02\r
+RH_SRAM_1MBITS equ 0x03\r
+RH_SRAM_2MBITS equ 0x04\r
+RH_SRAM_1KBITS equ 0x10\r
+RH_SRAM_16KBITS equ 0x20\r
+RH_SRAM_8KBITS equ 0x50\r
+\r
+RH_WS_MONO equ 0x00\r
+RH_WS_COLOR equ 0x01\r
+\r
+RH_NO_RTC equ 0x00\r
+RH_RTC equ 0x01\r
+\r
+RH_HORIZONTAL equ (0x04 + 0x00)\r
+RH_VERTICAL equ (0x04 + 0x01)\r
+\r
+\r
+\r
+;-----------------\r
+; Memory Address\r
+\r
+WS_RAM_BASE equ 0x0000\r
+WS_TILE_BANK equ 0x2000\r
+WS_STACK equ WS_TILE_BANK-2\r
+\r
+WSC_TILE_BANK1 equ 0x4000\r
+WSC_TILE_BANK2 equ 0x8000\r
+WSC_RAM_BASE2 equ 0xC000\r
+WSC_PALETTES equ 0xFE00\r
+WSC_STACK equ WSC_PALETTES-2\r
+\r
+MAP_SIZE equ 0x800\r
+SPR_TABLE_SIZE equ 0x200\r
+\r
+\r
+\r
+;-------------\r
+; Interrupts\r
+\r
+INTVEC_HBLANK_TIMER equ 7\r
+INTVEC_VBLANK_START equ 6\r
+INTVEC_VBLANK_TIMER equ 5\r
+INTVEC_DRAWING_LINE equ 4\r
+INTVEC_SERIAL_RECEIVE equ 3\r
+INTVEC_RTC_ALARM equ 2\r
+INTVEC_KEY_PRESS equ 1\r
+INTVEC_SERIAL_SEND equ 0\r
+\r
+\r
+\r
+;-----------------\r
+; Useful Defines\r
+\r
+%define BG_CHR(tile,pal,bank,hflip,vflip) (((vflip) << 15) | ((hflip) << 14) | ((bank) << 13) | ((pal) << 9) | (tile))\r
+\r
+%macro ROM_HEADER 7 ; Label, Segment, DevID, WSType, RomSize, SRamSize, WSSpec\r
+ times ((64*1024)-16)-$+%1 db 0xFF\r
+\r
+ db 0xEA ; jmpf\r
+ dw %1 ; Label\r
+ dw %2 ; Segment\r
+ db 0x00\r
+\r
+ db %3 ; Developer ID\r
+ db %4\r
+ db 0x01 ; Cart number\r
+ db 0x00\r
+ db %5\r
+ db %6\r
+ db %7\r
+ db 0x00\r
+ dw 0x0000 ; Checksum\r
+%endmacro\r
+\r
+%macro PADDING 1 ; Number of Segment\r
+ times (%1*64*1024) db 0xFF\r
+%endmacro\r
+\r
+SCREEN_WIDTH equ 224\r
+SCREEN_HEIGHT equ 144\r
+SCREEN_TWIDTH equ (SCREEN_WIDTH / 8)\r
+SCREEN_THEIGHT equ (SCREEN_HEIGHT / 8)\r
+MAP_WIDTH equ 256\r
+MAP_HEIGHT equ 256\r
+MAP_TWIDTH equ (MAP_WIDTH / 8)\r
+MAP_THEIGHT equ (MAP_HEIGHT / 8)\r
+\r
+\r
+\r
+;-----------------------------------\r
+; I/O Ports and associated equates\r
+\r
+IO_DISPLAY_CTRL equ 0x00\r
+BG_ON equ 0x01\r
+BG_OFF equ 0x00\r
+FG_ON equ 0x02\r
+FG_OFF equ 0x00\r
+SPR_ON equ 0x04\r
+SPR_OFF equ 0x00\r
+SPR_WIN_ON equ 0x08\r
+SPR_WIN_OFF equ 0x00\r
+FG_IN_OUT_WIN equ 0x00\r
+FG_IN_WIN equ 0x10\r
+FG_OUT_WIN equ 0x30\r
+\r
+IO_BG_PAL equ 0x01\r
+%define BG_COLOR(a) (a)\r
+%define BG_PAL(a) (a << 4)\r
+\r
+IO_CUR_LINE equ 0x02\r
+IO_LINE_COMP equ 0x03\r
+\r
+IO_SPR_TABLE equ 0x04\r
+%define SPR_TABLE(a) (a >> 9) ; Sprite Table Address must be 512 bytes aligned !\r
+\r
+IO_SPR_START equ 0x05\r
+IO_SPR_STOP equ 0x06\r
+\r
+IO_FGBG_MAP equ 0x07\r
+%define FG_MAP(a) ((a >> 11) << 4) ; FG Map Address must be 2048 bytes aligned !\r
+%define BG_MAP(a) (a >> 11) ; BG Map Address must be 2048 bytes aligned !\r
+\r
+IO_FG_WIN_X0 equ 0x08\r
+IO_FG_WIN_Y0 equ 0x09\r
+IO_FG_WIN_X1 equ 0x0A\r
+IO_FG_WIN_Y1 equ 0x0B\r
+\r
+IO_SPR_WIN_X0 equ 0x0C\r
+IO_SPR_WIN_Y0 equ 0x0D\r
+IO_SPR_WIN_X1 equ 0x0E\r
+IO_SPR_WIN_Y1 equ 0x0F\r
+\r
+IO_BG_X equ 0x10\r
+IO_BG_Y equ 0x11\r
+\r
+IO_FG_X equ 0x12\r
+IO_FG_Y equ 0x13\r
+\r
+IO_LCD_CTRL equ 0x14\r
+LCD_ON equ 0x01\r
+LCD_OFF equ 0x00\r
+\r
+IO_LCD_ICONS equ 0x15\r
+LCD_ICON_SLEEP equ 0x01\r
+LCD_ICON_VERTI equ 0x02\r
+LCD_ICON_HORIZ equ 0x04\r
+LCD_ICON_DOT1 equ 0x08\r
+LCD_ICON_DOT2 equ 0x10\r
+LCD_ICON_DOT3 equ 0x20\r
+\r
+IO_PALSHADE_10 equ 0x1C\r
+IO_PALSHADE_32 equ 0x1D\r
+IO_PALSHADE_54 equ 0x1E\r
+IO_PALSHADE_76 equ 0x1F\r
+\r
+IO_WS_PAL_00 equ 0x20\r
+IO_WS_PAL_01 equ 0x21\r
+IO_WS_PAL_10 equ 0x22\r
+IO_WS_PAL_11 equ 0x23\r
+IO_WS_PAL_20 equ 0x24\r
+IO_WS_PAL_21 equ 0x25\r
+IO_WS_PAL_30 equ 0x26\r
+IO_WS_PAL_31 equ 0x27\r
+IO_WS_PAL_40 equ 0x28\r
+IO_WS_PAL_41 equ 0x29\r
+IO_WS_PAL_50 equ 0x2A\r
+IO_WS_PAL_51 equ 0x2B\r
+IO_WS_PAL_60 equ 0x2C\r
+IO_WS_PAL_61 equ 0x2D\r
+IO_WS_PAL_70 equ 0x2E\r
+IO_WS_PAL_71 equ 0x2F\r
+IO_WS_PAL_80 equ 0x30\r
+IO_WS_PAL_81 equ 0x31\r
+IO_WS_PAL_90 equ 0x32\r
+IO_WS_PAL_91 equ 0x33\r
+IO_WS_PAL_A0 equ 0x34\r
+IO_WS_PAL_A1 equ 0x35\r
+IO_WS_PAL_B0 equ 0x36\r
+IO_WS_PAL_B1 equ 0x37\r
+IO_WS_PAL_C0 equ 0x38\r
+IO_WS_PAL_C1 equ 0x39\r
+IO_WS_PAL_D0 equ 0x3A\r
+IO_WS_PAL_D1 equ 0x3B\r
+IO_WS_PAL_E0 equ 0x3C\r
+IO_WS_PAL_E1 equ 0x3D\r
+IO_WS_PAL_F0 equ 0x3E\r
+IO_WS_PAL_F1 equ 0x3F\r
+\r
+IOw_DMA_SRC equ 0x40\r
+IO_DMA_SRC_BANK equ 0x42\r
+IO_DMA_DST_BANK equ 0x43\r
+IOw_DMA_DST equ 0x44\r
+IOw_DMA_SIZE equ 0x46\r
+IO_DMA_CTRL equ 0x48\r
+DMA_START equ 0x80\r
+DMA_CHECK equ 0x80\r
+\r
+IOw_SNDDMA_SRC equ 0x4A\r
+IO_SNDDMA_BANK equ 0x4C\r
+IOw_SNDDMA_SIZE equ 0x4E\r
+IO_SNDDMA_CTRL equ 0x52\r
+\r
+IO_VIDEO_MODE equ 0x60\r
+VMODE_16C_CHK equ 0xE0 ; 16 colors per tile chunky mode\r
+VMODE_16C_PLN equ 0xC0 ; 16 colors per tile planar mode\r
+VMODE_4C equ 0x40 ; 4 colors per tile color\r
+VMODE_4C_MONO equ 0x00 ; 4 colors per tile mono\r
+VMODE_CLEANINIT equ 0x0C ; (?) from FF2\r
+\r
+IOw_AUDIO1_FREQ equ 0x80 ; Frequency\r
+IOw_AUDIO2_FREQ equ 0x82\r
+IOw_AUDIO3_FREQ equ 0x84\r
+IOw_AUDIO4_FREQ equ 0x86\r
+\r
+IO_AUDIO1_VOL equ 0x88 ; Volume\r
+IO_AUDIO2_VOL equ 0x89\r
+IO_AUDIO3_VOL equ 0x8A\r
+IO_AUDIO4_VOL equ 0x8B\r
+\r
+IO_AUDIO_SWEEP_VAL equ 0x8C\r
+IO_AUDIO_SWEEP_STEP equ 0x8D\r
+\r
+IO_AUDIO_NOISE_CTRL equ 0x8E\r
+%define NOISE_TYPE(a) (a)\r
+NOISE_RESET equ 0x08\r
+NOISE_ENABLE equ 0x10\r
+\r
+IO_AUDIO_SAMPLE equ 0x8F ; Sample location\r
+%define AUDIO_SAMPLE(a) (a >> 6)\r
+\r
+IO_AUDIO_CTRL equ 0x90\r
+AUDIO_1_ON equ 0x01\r
+AUDIO_1_OFF equ 0x00\r
+AUDIO_2_ON equ 0x02\r
+AUDIO_2_OFF equ 0x00\r
+AUDIO_3_ON equ 0x04\r
+AUDIO_3_OFF equ 0x00\r
+AUDIO_4_ON equ 0x08\r
+AUDIO_4_OFF equ 0x00\r
+AUDIO_2_VOICE equ 0x20\r
+AUDIO_3_SWEEP equ 0x40\r
+AUDIO_4_NOISE equ 0x80\r
+\r
+IO_AUDIO_OUTPUT equ 0x91\r
+AUDIO_OUT_MONO equ 0x01\r
+AUDIO_OUT_STEREO equ 0x08\r
+%define AUDIO_OUT_VOLUME(a) ((a & 0x03) << 1)\r
+\r
+IOw_AUDIO_NOISE_CNT equ 0x92\r
+IO_AUDIO_VOLUME equ 0x94 ; Global Volume (4 bits)\r
+\r
+IO_HARDWARE_TYPE equ 0xA0\r
+WS_COLOR equ 0x02\r
+WS_MONO equ 0x00\r
+\r
+IO_TIMER_CTRL equ 0xA2\r
+HBLANK_TIMER_ON equ 0x01\r
+HBLANK_TIMER_OFF equ 0x00\r
+HBLANK_TIMER_MODE_ONESHOT equ 0x00\r
+HBLANK_TIMER_MODE_AUTOPRESET equ 0x02\r
+VBLANK_TIMER_ON equ 0x04\r
+VBLANK_TIMER_OFF equ 0x00\r
+VBLANK_TIMER_MODE_ONESHOT equ 0x00\r
+VBLANK_TIMER_MODE_AUTOPRESET equ 0x08\r
+\r
+IOw_HBLANK_FREQ equ 0xA4\r
+IOw_VBLANK_FREQ equ 0xA6\r
+\r
+IO_HBLANK_CNT1 equ 0xA8 ; Hblank Counter - 1/12000s\r
+IO_HBLANK_CNT2 equ 0xA9 ; Hblank Counter - 1/(12000>>8)s\r
+IO_VBLANK_CNT1 equ 0xAA ; Vblank Counter - 1/75s\r
+IO_VBLANK_CNT2 equ 0xAB ; Vblank Counter - 1/(75>>8)s\r
+\r
+IO_INT_BASE equ 0xB0\r
+INT_BASE equ 0x20\r
+\r
+IO_COMM_DATA equ 0xB1 ; Communication byte\r
+\r
+IO_INT_ENABLE equ 0xB2\r
+INT_HBLANK_TIMER equ 0x80\r
+INT_VBLANK_START equ 0x40\r
+INT_VBLANK_TIMER equ 0x20\r
+INT_DRAWING_LINE equ 0x10\r
+INT_SERIAL_RECEIVE equ 0x08\r
+INT_RTC_ALARM equ 0x04\r
+INT_KEY_PRESS equ 0x02\r
+INT_SERIAL_SEND equ 0x01\r
+\r
+IO_COMM_DIR equ 0xB3 ; Communication direction\r
+COMM_RECEIVE_INT_GEN equ 0x80\r
+COMM_SPEED_9600 equ 0x00\r
+COMM_SPEED_38400 equ 0x40\r
+COMM_SEND_INT_GEN equ 0x20\r
+COMM_SEND_COMPLETE equ 0x04\r
+COMM_ERROR equ 0x02\r
+COMM_RECEIVE_COMPLETE equ 0x01\r
+\r
+IO_KEYPAD equ 0xB5\r
+KEYPAD_READ_ARROWS_V equ 0x10\r
+KEYPAD_READ_ARROWS_H equ 0x20\r
+KEYPAD_READ_BUTTONS equ 0x40\r
+PAD_UP equ 0x01\r
+PAD_RIGHT equ 0x02\r
+PAD_DOWN equ 0x04\r
+PAD_LEFT equ 0x08\r
+PAD_START equ 0x02\r
+PAD_A equ 0x04\r
+PAD_B equ 0x08\r
+\r
+IO_INT_ACK equ 0xB6 ; See IO_INT_ENABLE equates for values\r
+\r
+IOw_INTERNAL_EEPROM_DATA equ 0xBA\r
+IOw_INTERNAL_EEPROM_ADDRESS equ 0xBC\r
+\r
+IOw_INTERNAL_EEPROM_CTRL equ 0xBE\r
+IEEPROM_INIT equ 0x80\r
+IEEPROM_PROTECT equ 0x40\r
+IEEPROM_WRITE equ 0x20\r
+IEEPROM_READ equ 0x10\r
+IEEPROM_WRITE_COMPLETE equ 0x02\r
+IEEPROM_READ_COMPLETE equ 0x01\r
+\r
+IO_ROM_BASE_BANK equ 0xC0\r
+IO_SRAM_BANK equ 0xC1\r
+IO_ROM_BANK_SEGMENT2 equ 0xC2\r
+IO_ROM_BANK_SEGMENT3 equ 0xC3\r
+\r
+IO_RTC_COMMAND equ 0xCA\r
+RTC_COMMAND_RESET equ 0x10\r
+RTC_COMMAND_ALARM equ 0x12\r
+RTC_COMMAND_SET_TIME equ 0x14\r
+RTC_COMMAND_GET_TIME equ 0x15\r
+RTC_COMMAND_ACK equ 0x80\r
+\r
+IO_RTC_DATA equ 0xCB\r