X-Git-Url: https://robinkrens.nl/gitweb/?a=blobdiff_plain;f=lib%2Fregfunc.c;h=2e2468927f4213e352249b39c99c0aeb52aab1d2;hb=fac4700036ceaafe0d4a2b40d4c9f590d3c407b7;hp=f5bc5391583a9aad79663e8569d6c140ba135423;hpb=43b1749173f70bdf67884d920b93f6a5b1f19a1d;p=cortex-from-scratch diff --git a/lib/regfunc.c b/lib/regfunc.c index f5bc539..2e24689 100644 --- a/lib/regfunc.c +++ b/lib/regfunc.c @@ -17,8 +17,10 @@ #include #include -#include +#include +#include +#include // register set bit at position void rsetbit(volatile uint32_t * reg, short pos) { @@ -48,38 +50,6 @@ void rwrite(volatile uint32_t * reg, uint32_t val) { } -/* DEPRECATED write value (uint8_t) to register -void regw_u8(volatile uint32_t * reg, uint8_t val, short shift, short flag) { - - switch(flag) { - case OWRITE: - *reg = (val << shift); - break; - case SETBIT: - *reg = *reg | (val << shift); - break; - case CLRBIT: - *reg = *reg & ~(val << shift); - break; - } -} */ - -/* DEPRECATED write value (uint32_t) to register -void regw_u32(volatile uint32_t * reg, uint32_t val, short shift, short flag) { - - switch(flag) { - case OWRITE: - *reg = (val << shift); - break; - case SETBIT: - *reg = *reg | (val << shift); - break; - case CLRBIT: - *reg = *reg & ~(val << shift); - break; - } -} */ - /* Deprecated use printf instead char hexbuf[8]; char * regtohex(uint32_t addr) { @@ -127,3 +97,26 @@ uint32_t hextoreg(char * a) { } +/* Busy-loop block implementation. Each iteration will take 3 CPU cycles. + * Of course, when interrupts are enabled, the exact delay time will be + * uncertain. + * + * Example: for a standard STM32x config board (8MHz) the maximum delay is + * 0xFFFF * (1/8,000,000) * 3 = 24.58ms + * */ +static void __block(uint16_t count) { + + asm volatile("b1: subs %0, %1, #1" "\n\t" + "bne b1" : "=r" (count) : "r" (count)); +} + +/* Delay us microsecond + * Note: delay includes setup time (about 4 clockcycles), so is quite + * inaccurate */ +void _block(uint16_t us) { + + uint16_t count = (us/3) * CLKSPEED_MHZ; // x cycles + __block(count); + +} +